A theoretical approach to estimation of bounds on power consumption in digital multipliers

Janardhan H. Satyanarayana, Keshab K. Parhi

Research output: Contribution to journalArticle

12 Scopus citations


This paper presents a systematic theoretical approach for the analysis of bounds on power consumption in digital multipliers. This is because in many applications the maximum value of power consumption and not just the average power may be of importance to the designer. The maximum values can be used to predict the maximum battery life in portable applications and also determine the nature of heat sinks in nonportable applications. The proposed approach involves the development of state transition diagrams (stds) for the subcircuits making up the digital multipliers. The std is comprised of states and edges, with the edges representing a transition (switching activity) from one state to another in the subcircuit. Then, maximum (minimum) energy values associated with the edges constituting the stds are used to derive the upper (lower) bound. The multipliers analyzed in this paper include the Baugh Wooley multiplier, the binary tree multiplier, and the Wallace tree multiplier. The analysis is performed for both nonpipelined and p-bit-level pipelined multipliers. It is theoretically shown that there is a significant reduction in upper bound as p is decreased, with the lower bound being unaffected by the level of bit-pipelining. Experimental results are presented to show that the average power consumption values indeed lie within the predicted theoretical bounds, and that the theoretical upper bounds are quite tight.

Original languageEnglish (US)
Pages (from-to)473-481
Number of pages9
JournalIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Issue number6
StatePublished - Dec 1 1997



  • Bounds
  • Low power
  • Multipliers
  • Pipelining
  • Theoretical

Cite this