### Abstract

A systematic unfolding transformation technique for transforming bit-serial architectures into equivalent digit-serial ones is presented. The novel feature of the unfolding technique lies in the generation of functionally correct control circuits in the digit-serial architectures. For some applications bit-serial architectures may be too slow, and bit-parallel architectures may be faster than necessary and may require too much hardware. The desired sample rate in these applications can be achieved using the digit-serial approach, where multiple bits of a sample are processed in a single clock cycle. The number of bits processed in one clock cycle in the digit-serial systems is referred to as the digit size; the digit size can be any arbitrary integer (the digit size was restricted to be a divisor of wordlength in past ad hoc designs). Digit-serial implementation of two's complement adders and multipliers is described. Least-significant-bit-first bit-serial implementation of two's complement division, square-root, and compare-select operations are presented, and the corresponding digit-serial architectures for these operations are obtained using the unfolding algorithm. Unfolding of multiple-rate operations (such as interpolators and decimators) is also addressed.

Original language | English (US) |
---|---|

Pages (from-to) | 358-375 |

Number of pages | 18 |

Journal | IEEE transactions on circuits and systems |

Volume | 38 |

Issue number | 4 |

DOIs | |

State | Published - Apr 1 1991 |

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**A systematic approach for design of digit-serial signal processing architectures.** / Parhi, Keshab K.

Research output: Contribution to journal › Article

*IEEE transactions on circuits and systems*, vol. 38, no. 4, pp. 358-375. https://doi.org/10.1109/31.75394

}

TY - JOUR

T1 - A systematic approach for design of digit-serial signal processing architectures

AU - Parhi, Keshab K

PY - 1991/4/1

Y1 - 1991/4/1

N2 - A systematic unfolding transformation technique for transforming bit-serial architectures into equivalent digit-serial ones is presented. The novel feature of the unfolding technique lies in the generation of functionally correct control circuits in the digit-serial architectures. For some applications bit-serial architectures may be too slow, and bit-parallel architectures may be faster than necessary and may require too much hardware. The desired sample rate in these applications can be achieved using the digit-serial approach, where multiple bits of a sample are processed in a single clock cycle. The number of bits processed in one clock cycle in the digit-serial systems is referred to as the digit size; the digit size can be any arbitrary integer (the digit size was restricted to be a divisor of wordlength in past ad hoc designs). Digit-serial implementation of two's complement adders and multipliers is described. Least-significant-bit-first bit-serial implementation of two's complement division, square-root, and compare-select operations are presented, and the corresponding digit-serial architectures for these operations are obtained using the unfolding algorithm. Unfolding of multiple-rate operations (such as interpolators and decimators) is also addressed.

AB - A systematic unfolding transformation technique for transforming bit-serial architectures into equivalent digit-serial ones is presented. The novel feature of the unfolding technique lies in the generation of functionally correct control circuits in the digit-serial architectures. For some applications bit-serial architectures may be too slow, and bit-parallel architectures may be faster than necessary and may require too much hardware. The desired sample rate in these applications can be achieved using the digit-serial approach, where multiple bits of a sample are processed in a single clock cycle. The number of bits processed in one clock cycle in the digit-serial systems is referred to as the digit size; the digit size can be any arbitrary integer (the digit size was restricted to be a divisor of wordlength in past ad hoc designs). Digit-serial implementation of two's complement adders and multipliers is described. Least-significant-bit-first bit-serial implementation of two's complement division, square-root, and compare-select operations are presented, and the corresponding digit-serial architectures for these operations are obtained using the unfolding algorithm. Unfolding of multiple-rate operations (such as interpolators and decimators) is also addressed.

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U2 - 10.1109/31.75394

DO - 10.1109/31.75394

M3 - Article

AN - SCOPUS:0026140187

VL - 38

SP - 358

EP - 375

JO - IEEE Transactions on Circuits and Systems

JF - IEEE Transactions on Circuits and Systems

SN - 0098-4094

IS - 4

ER -