A supply-noise sensitivity tracking PLL in 32 nm SOI featuring a deep trench capacitor based loop filter

Keyphrases

• Supply Noise 100%
• Loop Filter 100%
• Noise Sensitivity 100%
• Deep Trench Capacitor 100%
• Capacitor-based 100%
• Adaptive PLL 100%
• Clock Data Compensation 66%
• Ultra-high Density 33%
• Proposed Design 33%
• Operating Conditions 33%
• Operating Frequency 33%
• Path Delay 33%
• Operating Speed 33%
• Fmax 33%
• Timing Error 33%
• Reduced Dynamics 33%
• Tracking Loop 33%
• Compensation Effect 33%
• PLL Design 33%
• Clock Period 33%
• Dynamic Power Consumption 33%
• Critical Path Replica 33%
• Replica Circuit 33%
• Clock Path 33%
• Resonant Power Supply Noise 33%

Engineering

• Phase Locked Loop 100%
• Noise Sensitivity 100%
• Loop Filter 100%
• Electric Power Utilization 14%
• One Step 14%
• Operating Frequency 14%
• Operating Speed 14%
• Tracking Loop 14%
• Iso 14%
• Critical Path 14%
• Clock Period 14%