A supply-noise sensitivity tracking PLL in 32 nm SOI featuring a deep trench capacitor based loop filter

An adaptive PLL that maximizes the timing compensation between clock and data, commonly referred to as the clock data compensation effect, is demonstrated in 32 nm SOI. A number of previous adaptive PLL designs have successfully proven that processor operating speed can be improved by modulating the clock path delay or the PLL output clock period using the resonant supply noise. In this work, we take the adaptive PLL concept one step further by achieving optimal clock data compensation across a wide range of PVT and operating conditions. This was accomplished by an automated supply-noise sensitivity tracking loop which constantly monitors any timing errors occurring in a critical path replica circuit. Compared to a conventional PLL, the proposed design achieves up to a 15.6% improvement in processor Fmax or a 9.8% reduced dynamic power consumption under an iso-operating frequency for a realistic supply noise. Additionally, a 92.1% reduction in PLL area was achieved by employing ultra-high density deep trench capacitors in the loop filter.