A sub-2.5ns frequency-hopped quadrature frequency synthesizer in 0.13-μm technology

Narasimha Lanka, Satwik Patnaik, Ramesh Harjani

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

This paper presents a fast-hopping frequency synthesizer architecture with quadrature outputs, based on sub-harmonic injection-locking, that is compliant with Wireless-USB/WiMedia specifications. The synthesizer features a cross-coupled quadrature digitally-controlled oscillator, that is injection locked to a sub-harmonic frequency. On-chip mixers have been implemented to measure the quadrature accuracy of the outputs. The overall architecture is a CMOS-only implementation and has been fabricated in 0.13-μm SiGe BiCMOS process. Measurement results indicate lock-times of less than 2.5 ns, a locked phase noise of -114 dBc/Hz at 1 MHz offset and a quadrature accuracy of better than 0.5°. The frequency synthesizer (excluding output buffers) occupies an area of 0.27 mm2 and consumes 14.5 mW of power. The best and worst case spur suppression achieved are 47 and 31 dB, respectively. This is the lowest power fast-hopping quadrature frequency synthesizer that has been reported to date.

Original languageEnglish (US)
Title of host publication2009 IEEE Custom Integrated Circuits Conference, CICC '09
Pages57-60
Number of pages4
DOIs
StatePublished - Dec 1 2009
Event2009 IEEE Custom Integrated Circuits Conference, CICC '09 - San Jose, CA, United States
Duration: Sep 13 2009Sep 16 2009

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Other

Other2009 IEEE Custom Integrated Circuits Conference, CICC '09
CountryUnited States
CitySan Jose, CA
Period9/13/099/16/09

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