A sub-0.9V logic-compatible embedded DRAM with boosted 3T gain cell, regulated bit-line write scheme and PVT-tracking read reference bias

Ki Chul Chun; Pulkit Jain; Jung Hwa Lee; Chris H. Kim

A sub-0.9V logic-compatible embedded DRAM with boosted 3T gain cell, regulated bit-line write scheme and PVT-tracking read reference bias

Ki Chul Chun
, Pulkit Jain
, Jung Hwa Lee
, Chris H. Kim

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

38 Scopus citations

Abstract

Circuit techniques for enabling a sub-0.9V logic-compatible embedded DRAM (eDRAM) are presented. A boosted 3T gain cell increases read margin, enhances read speed and improves data retention time. A regulated bit-line write scheme and a read reference bias generator are proposed to cope with write disturbance issues and PVT variations. Measurement results from a 64kb eDRAM test chip implemented in a 65nm low-leakage CMOS process demonstrate the effectiveness of the proposed techniques.

Original language	English (US)
Title of host publication	2009 Symposium on VLSI Circuits
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	134-135
Number of pages	2
ISBN (Print)	9784863480018
State	Published - 2009
Event	2009 Symposium on VLSI Circuits, VLSIC 2009 - Kyoto, Japan Duration: Jun 16 2009 → Jun 18 2009

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
ISSN (Print)	2158-5601
ISSN (Electronic)	2158-5636

Conference

Conference	2009 Symposium on VLSI Circuits, VLSIC 2009
Country/Territory	Japan
City	Kyoto
Period	6/16/09 → 6/18/09

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Chun, K. C., Jain, P., Lee, J. H., & Kim, C. H. (2009). A sub-0.9V logic-compatible embedded DRAM with boosted 3T gain cell, regulated bit-line write scheme and PVT-tracking read reference bias. In 2009 Symposium on VLSI Circuits (pp. 134-135). Article 5205419 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). Institute of Electrical and Electronics Engineers Inc..

A sub-0.9V logic-compatible embedded DRAM with boosted 3T gain cell, regulated bit-line write scheme and PVT-tracking read reference bias. / Chun, Ki Chul; Jain, Pulkit; Lee, Jung Hwa et al.
2009 Symposium on VLSI Circuits. Institute of Electrical and Electronics Engineers Inc., 2009. p. 134-135 5205419 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Chun, KC, Jain, P, Lee, JH & Kim, CH 2009, A sub-0.9V logic-compatible embedded DRAM with boosted 3T gain cell, regulated bit-line write scheme and PVT-tracking read reference bias. in 2009 Symposium on VLSI Circuits., 5205419, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Institute of Electrical and Electronics Engineers Inc., pp. 134-135, 2009 Symposium on VLSI Circuits, VLSIC 2009, Kyoto, Japan, 6/16/09.

@inproceedings{46d471a1a7ca46aebcc46f62a75dc32f,

title = "A sub-0.9V logic-compatible embedded DRAM with boosted 3T gain cell, regulated bit-line write scheme and PVT-tracking read reference bias",

abstract = "Circuit techniques for enabling a sub-0.9V logic-compatible embedded DRAM (eDRAM) are presented. A boosted 3T gain cell increases read margin, enhances read speed and improves data retention time. A regulated bit-line write scheme and a read reference bias generator are proposed to cope with write disturbance issues and PVT variations. Measurement results from a 64kb eDRAM test chip implemented in a 65nm low-leakage CMOS process demonstrate the effectiveness of the proposed techniques.",

author = "Chun, \{Ki Chul\} and Pulkit Jain and Lee, \{Jung Hwa\} and Kim, \{Chris H.\}",

year = "2009",

language = "English (US)",

isbn = "9784863480018",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "134--135",

booktitle = "2009 Symposium on VLSI Circuits",

note = "2009 Symposium on VLSI Circuits, VLSIC 2009 ; Conference date: 16-06-2009 Through 18-06-2009",

}

TY - GEN

T1 - A sub-0.9V logic-compatible embedded DRAM with boosted 3T gain cell, regulated bit-line write scheme and PVT-tracking read reference bias

AU - Chun, Ki Chul

AU - Jain, Pulkit

AU - Lee, Jung Hwa

AU - Kim, Chris H.

PY - 2009

Y1 - 2009

N2 - Circuit techniques for enabling a sub-0.9V logic-compatible embedded DRAM (eDRAM) are presented. A boosted 3T gain cell increases read margin, enhances read speed and improves data retention time. A regulated bit-line write scheme and a read reference bias generator are proposed to cope with write disturbance issues and PVT variations. Measurement results from a 64kb eDRAM test chip implemented in a 65nm low-leakage CMOS process demonstrate the effectiveness of the proposed techniques.

AB - Circuit techniques for enabling a sub-0.9V logic-compatible embedded DRAM (eDRAM) are presented. A boosted 3T gain cell increases read margin, enhances read speed and improves data retention time. A regulated bit-line write scheme and a read reference bias generator are proposed to cope with write disturbance issues and PVT variations. Measurement results from a 64kb eDRAM test chip implemented in a 65nm low-leakage CMOS process demonstrate the effectiveness of the proposed techniques.

UR - https://www.scopus.com/pages/publications/70449435054

UR - https://www.scopus.com/pages/publications/70449435054#tab=citedBy

M3 - Conference contribution

AN - SCOPUS:70449435054

SN - 9784863480018

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - 134

EP - 135

BT - 2009 Symposium on VLSI Circuits

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2009 Symposium on VLSI Circuits, VLSIC 2009

Y2 - 16 June 2009 through 18 June 2009

ER -

A sub-0.9V logic-compatible embedded DRAM with boosted 3T gain cell, regulated bit-line write scheme and PVT-tracking read reference bias

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