A sub-0.9V logic-compatible embedded DRAM with boosted 3T gain cell, regulated bit-line write scheme and PVT-tracking read reference bias

Ki Chul Chun, Pulkit Jain, Jung Hwa Lee, Chris H. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

34 Scopus citations

Abstract

Circuit techniques for enabling a sub-0.9V logic-compatible embedded DRAM (eDRAM) are presented. A boosted 3T gain cell increases read margin, enhances read speed and improves data retention time. A regulated bit-line write scheme and a read reference bias generator are proposed to cope with write disturbance issues and PVT variations. Measurement results from a 64kb eDRAM test chip implemented in a 65nm low-leakage CMOS process demonstrate the effectiveness of the proposed techniques.

Original languageEnglish (US)
Title of host publication2009 Symposium on VLSI Circuits
Pages134-135
Number of pages2
StatePublished - Nov 18 2009
Event2009 Symposium on VLSI Circuits - Kyoto, Japan
Duration: Jun 16 2009Jun 18 2009

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2009 Symposium on VLSI Circuits
CountryJapan
CityKyoto
Period6/16/096/18/09

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    Chun, K. C., Jain, P., Lee, J. H., & Kim, C. H. (2009). A sub-0.9V logic-compatible embedded DRAM with boosted 3T gain cell, regulated bit-line write scheme and PVT-tracking read reference bias. In 2009 Symposium on VLSI Circuits (pp. 134-135). [5205419] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).