A stochastic reconfigurable architecture for fault-tolerant computation with sequential logic

Peng Li, Weikang Qian, David J. Lilja

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Scopus citations

Abstract

Computation performed on stochastic bit streams is less efficient than that based on a binary radix because of its long latency. However, for certain complex arithmetic operations, computation on stochastic bit streams can consume less energy and tolerate more soft errors. In addition, the latency issue could be solved by using a faster clock frequency or in combination with a parallel processing approach. To take advantage of this computing technique, previous work proposed a combinational logic-based reconfigurable architecture to perform complex arithmetic operations on stochastic streams of bits. In this paper, we enhance and extend this reconfigurable architecture using sequential logic. Compared to the previous approach, the proposed reconfigurable architecture takes less hardware area and consumes less energy, while achieving the same performance in terms of processing time and fault-tolerance.

Original languageEnglish (US)
Title of host publication2012 IEEE 30th International Conference on Computer Design, ICCD 2012
Pages303-308
Number of pages6
DOIs
StatePublished - Dec 1 2012
Event2012 IEEE 30th International Conference on Computer Design, ICCD 2012 - Montreal, QC, Canada
Duration: Sep 30 2012Oct 3 2012

Publication series

NameProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
ISSN (Print)1063-6404

Other

Other2012 IEEE 30th International Conference on Computer Design, ICCD 2012
Country/TerritoryCanada
CityMontreal, QC
Period9/30/1210/3/12

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