Unlike devices built using wafers, single nanoparticle semiconductor devices made from single-crystal particles would allow the construction of high performance three-dimensional circuits and the integration of otherwise chemically and structurally incompatible single-crystal materials on virtually any substrate. This would dramatically reduce interconnect delay in integrated circuits, eliminate substrate parasitic effects, and allow the monolithic integration of complex systems. The production of cubic, highly perfect single crystal Si nanoparticles has been achieved using a constricted capacitively coupled plasma 1,2. The discharge was a striated, high-luminosity plasma filament that rotated close to the wall at ∼ 150 Hz. The particles were highly monodisperse with a peak size of 35 nm and a standard deviation of 4.7 nm. TEM studies showed that the particles were perfect single crystals with (100) faces. Elemental analysis of the thin (∼2 nm) amorphous surface layer showed it to be an oxide of silicon. High-resolution images of the particles were taken using a spherical-aberration (C s) corrected TEM. This thin layer is a distinct, abrupt film which appears to be a native oxide. To form electrical contacts, nanoparticles have been deposited on metallic or heavily doped silicon substrates and covered with an insulator. Chemical mechanical polishing was used to planarize the top. Different sized squares were patterned using a dark field mask. Dry etching was used to expose the top of the particles. Finally a top electrode was deposited and lifted off, forming a Schottky contact. This process allows one to make self aligned contacts to many particles in parallel avoiding the need for high resolution lithography to a single particle. By measuring the temperature dependence of these characteristics, it was determined that the current is limited to a surface channel at low voltage. At high voltage the devices demonstrate space charge limited current. Traps appear to be dominated by surface states on the particle. The process used to make these metal-semiconductor-metal devices was then extended to a Schottky barrier, vertical flow, surround-gate, field effect transistor. This is a challenging proposition since, unlike nanotube devices, all three dimensions on the nanoparticle are only a few tens of nanometers. To do this a gate layer was inserted between the upper and lower electrodes of the previous process by repeated deposition, polishing, and etchback steps. Both platinum and chromium have been used as the gate electrode. Early devices used an SiO 2 gate insulator; later devices employed HfO 2 which was found to significantly decrease gate leakage. The maximum temperature of the process was 400°C, making it compatible with use on top of existing CMOS wafers. The turn off characteristic shows an inverse slope of ∼70 mV/decade. A family of curves has been obtained. The low bias regime is clearly nonlinear, as one might expect for this type of structure. Saturation is not observed up to the highest voltages used. The device transconductance is roughly 80 μA/V per 35 nm particle or 6×10 6 amp/V-cm 2.