A simple technique to reduce clock jitter effects in continuous-time delta-sigma modulators

Hairong Chang, Hua Tang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

Continuous-time Delta-Sigma modulators are very sensitive to clock jitter effects. In this paper, we present a simple technique to reduce clock jitter effects. The technique employs two delayed elements to generate a feedback current waveform with a fixed-width return-to-zero time period, followed a fixed-width time period for active feedback, which is followed by another variable return-to-zero time period subject to clock jitter. It has been shown in the paper through behavioral simulation models that this technique is very effective to reduce independent clock jitter effects.

Original languageEnglish (US)
Title of host publication2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Pages1870-1873
Number of pages4
DOIs
StatePublished - Sep 19 2008
Event2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA, United States
Duration: May 18 2008May 21 2008

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

Other2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
CountryUnited States
CitySeattle, WA
Period5/18/085/21/08

Keywords

  • Clock jitter effects
  • Continuous-time
  • Delta-sigma modulator

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