Abstract
This brief presents a novel pipelined architecture to compute the fast Fourier transform of real input signals in a serial manner, i.e., one sample is processed per cycle. The proposed architecture, referred to as real-valued serial commutator, achieves full hardware utilization by mapping each stage of the fast Fourier transform (FFT) to a half-butterfly operation that operates on real input signals. Prior serial architectures to compute FFT of real signals only achieved 50% hardware utilization. Novel data-exchange and data-reordering circuits are also presented. The complete serial commutator architecture requires 2 2 N-2 real adders, 2 N-2 real multipliers, and N+9 2 N-19 real delay elements, where N represents the size of the FFT.
| Original language | English (US) |
|---|---|
| Article number | 8039527 |
| Pages (from-to) | 1693-1697 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
| Volume | 65 |
| Issue number | 11 |
| DOIs | |
| State | Published - Nov 2018 |
Bibliographical note
Funding Information:Manuscript received August 4, 2017; accepted September 4, 2017. Date of publication September 18, 2017; date of current version October 29, 2018. This work was supported by the Swedish ELLIIT Program. This brief was recommended by Associate Editor L.-P. Chau. (Corresponding author: Mario Garrido.) M. Garrido is with the Department of Electrical Engineering, Linköping University, 581 83 Linköping, Sweden (e-mail: mario.garrido.galvez@liu.se).
Publisher Copyright:
© 2004-2012 IEEE.
Keywords
- Fast Fourier transform (FFT)
- pipelined architecture
- real-valued signals
- serial commutator (SC)