A Serial Commutator Fast Fourier Architecture for Real-Valued Signals

Mario Garrido, Nanda K. Unnikrishnan, Keshab K Parhi

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

This brief presents a novel pipelined architecture to compute the fast Fourier transform of real input signals in a serial manner, i.e., one sample is processed per cycle. The proposed architecture, referred to as real-valued serial commutator, achieves full hardware utilization by mapping each stage of the fast Fourier transform (FFT) to a half-butterfly operation that operates on real input signals. Prior serial architectures to compute FFT of real signals only achieved 50% hardware utilization. Novel data-exchange and data-reordering circuits are also presented. The complete serial commutator architecture requires 2 2 N-2 real adders, 2 N-2 real multipliers, and N+9 2 N-19 real delay elements, where N represents the size of the FFT.

Original languageEnglish (US)
Article number8039527
Pages (from-to)1693-1697
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume65
Issue number11
DOIs
StatePublished - Nov 1 2018

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Electric commutators
Fast Fourier transforms
Hardware
Adders
Electronic data interchange
Networks (circuits)

Keywords

  • Fast Fourier transform (FFT)
  • pipelined architecture
  • real-valued signals
  • serial commutator (SC)

Cite this

A Serial Commutator Fast Fourier Architecture for Real-Valued Signals. / Garrido, Mario; Unnikrishnan, Nanda K.; Parhi, Keshab K.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 65, No. 11, 8039527, 01.11.2018, p. 1693-1697.

Research output: Contribution to journalArticle

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