A fully scalable light-weight integrate-and-fire neuromorphic core with brain-inspired leak and local lateral inhibition features is implemented in 65nm. The core computes the neural net algorithm entirely in the time domain using standard digital circuits. A parallel two-layer architecture realized using the proposed core achieves a 91% handwritten digit recognition accuracy. The 0.24mm2 neuromorphic core including 64 digitally controlled oscillator (DCO) circuits consumes 320.4μW per DCO at a maximum throughput of 746M pixels/s.
|Original language||English (US)|
|Title of host publication||38th Annual Custom Integrated Circuits Conference|
|Subtitle of host publication||A Showcase for Integrated Circuit Design in Silicon Hills, CICC 2017|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|State||Published - Jul 26 2017|
|Event||38th Annual Custom Integrated Circuits Conference, CICC 2017 - Austin, United States|
Duration: Apr 30 2017 → May 3 2017
|Name||Proceedings of the Custom Integrated Circuits Conference|
|Other||38th Annual Custom Integrated Circuits Conference, CICC 2017|
|Period||4/30/17 → 5/3/17|
Bibliographical noteFunding Information:
ACKNOWLEDGMENT This research was supported in part by NSF IGERT grant DGE-1069104.
© 2017 IEEE.
- Time-based circuits
- local lateral inhibition