A robust self-resetting CMOS 32-bit parallel adder

Gunok Jung, Venkat Sundarajan, Gerald E. Sobelman

Research output: Contribution to journalArticlepeer-review

9 Scopus citations


This paper presents new circuit configurations for a more robust and efficient form of self-resetting CMOS (SRCMOS). Prior structures for SRCMOS have very high performance but are difficult to design and are not robust over process, temperature and voltage variations. The new techniques replace delay chains with logical circuits that will create pulses at the correct times, independent of operational and environmental factors. These concepts are illustrated using a 32-bit parallel adder as a design example.

Original languageEnglish (US)
Pages (from-to)473-476
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - Jan 1 2002


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