A robust adaptive power line interference canceler VLSI architecture and ASIC for multichannel biopotential recording applications

This brief presents the very-large-scale integration (VLSI) architecture and application-specific integrated circuit of a robust algorithm for removing power line interference in multichannel biopotential recording. When compared with three similar interference removal methods, the proposed algorithm outperforms in terms of robustness and interference rejection performance. The proposed VLSI architecture is scalable with respect to the number of channels and/or harmonics. Further performance optimization is obtained through pipelining and resource-sharing techniques. A prototype was implemented in a 65-nm complementary metal-oxide-semiconductor process and validated against a golden model. Measurement results on different types of signal modalities show an average signal-to-noise ratio (SNR) improvement of 31 dB for input SNRs from ?20 to 20 dB and line frequencies of 45-65 Hz.