A Review of 3-Dimensional Wafer Level Stacked Backside Illuminated CMOS Image Sensor Process Technologies

Shou Gwo Wuu; Hsin Li Chen; Ho Ching Chien; Paul Enquist; R. Michael Guidash; John McCarten

doi:10.1109/TED.2022.3152977

A Review of 3-Dimensional Wafer Level Stacked Backside Illuminated CMOS Image Sensor Process Technologies

Shou Gwo Wuu
, Hsin Li Chen
, Ho Ching Chien
, Paul Enquist
, R. Michael Guidash
, John McCarten

Neurology

Research output: Contribution to journal › Review article › peer-review

21 Scopus citations

Abstract

Over the past 10 years, 3-dimensional (3-D) wafer-level stacked backside Illuminated (BSI) CMOS image sensors (CISs) have undergone rapid progress in development and performance and are now in mass production. This review paper covers the key processes and technology components of 3-D integrated BSI devices, as well as results from early devices fabricated and tested in 2007 and 2008. This article is divided into three main sections. Section II covers wafer-level bonding technology. Section III covers the key wafer fabrication process modules for BSI 3-D wafer-level stacking. Section IV presents the device results.

Original language	English (US)
Pages (from-to)	2766-2778
Number of pages	13
Journal	IEEE Transactions on Electron Devices
Volume	69
Issue number	6
DOIs	https://doi.org/10.1109/TED.2022.3152977
State	Published - Jun 1 2022

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Publisher Copyright:
© 1963-2012 IEEE.

Keywords

3-dimensional (3-D) stack
CMOS image sensor (CIS)
backside deep trench isolation (BDTI)
backside illuminated (BSI)
dark current
high-k film
hole sensor
hybrid stacking
near infrared response (NIR)
pMOS pixel
pyramid structure
thin down
wafer-level bonding
waferlevel stacking

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10.1109/TED.2022.3152977

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title = "A Review of 3-Dimensional Wafer Level Stacked Backside Illuminated CMOS Image Sensor Process Technologies",

abstract = "Over the past 10 years, 3-dimensional (3-D) wafer-level stacked backside Illuminated (BSI) CMOS image sensors (CISs) have undergone rapid progress in development and performance and are now in mass production. This review paper covers the key processes and technology components of 3-D integrated BSI devices, as well as results from early devices fabricated and tested in 2007 and 2008. This article is divided into three main sections. Section II covers wafer-level bonding technology. Section III covers the key wafer fabrication process modules for BSI 3-D wafer-level stacking. Section IV presents the device results.",

keywords = "3-dimensional (3-D) stack, CMOS image sensor (CIS), backside deep trench isolation (BDTI), backside illuminated (BSI), dark current, high-k film, hole sensor, hybrid stacking, near infrared response (NIR), pMOS pixel, pyramid structure, thin down, wafer-level bonding, waferlevel stacking",

author = "Wuu, \{Shou Gwo\} and Chen, \{Hsin Li\} and Chien, \{Ho Ching\} and Paul Enquist and \{Michael Guidash\}, R. and John McCarten",

note = "Publisher Copyright: {\textcopyright} 1963-2012 IEEE.",

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doi = "10.1109/TED.2022.3152977",

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AU - Enquist, Paul

AU - Michael Guidash, R.

AU - McCarten, John

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AB - Over the past 10 years, 3-dimensional (3-D) wafer-level stacked backside Illuminated (BSI) CMOS image sensors (CISs) have undergone rapid progress in development and performance and are now in mass production. This review paper covers the key processes and technology components of 3-D integrated BSI devices, as well as results from early devices fabricated and tested in 2007 and 2008. This article is divided into three main sections. Section II covers wafer-level bonding technology. Section III covers the key wafer fabrication process modules for BSI 3-D wafer-level stacking. Section IV presents the device results.

KW - 3-dimensional (3-D) stack

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KW - backside deep trench isolation (BDTI)

KW - backside illuminated (BSI)

KW - dark current

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ER -

A Review of 3-Dimensional Wafer Level Stacked Backside Illuminated CMOS Image Sensor Process Technologies

Abstract

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