TY - GEN
T1 - A retargetable and accurate methodology for logic-IP-internal electromigration assessment
AU - Jain, Palkesh
AU - Sapatnekar, Sachin S.
AU - Cortadella, Jordi
N1 - Publisher Copyright:
© 2015 IEEE.
Copyright:
Copyright 2015 Elsevier B.V., All rights reserved.
PY - 2015/3/11
Y1 - 2015/3/11
N2 - A new methodology for SoC-level logic-IP-internal EM verification is presented, which provides an on-the-fly retargeting capability for reliability constraints. This flexibility is available at the design verification stage, in the form of allowing arbitrary specifications (of lifetimes, temperatures, voltages and failure rates), as well as interoperability of IPs across foundries. The methodology is characterization- and reuse-based, and naturally incorporates complex effects such as clock gating and variable switching rates at different pins. The benefit from such a framework is demonstrated on a 28nm design, with close SPICE-correlation and verification in a retargeted reliability condition.
AB - A new methodology for SoC-level logic-IP-internal EM verification is presented, which provides an on-the-fly retargeting capability for reliability constraints. This flexibility is available at the design verification stage, in the form of allowing arbitrary specifications (of lifetimes, temperatures, voltages and failure rates), as well as interoperability of IPs across foundries. The methodology is characterization- and reuse-based, and naturally incorporates complex effects such as clock gating and variable switching rates at different pins. The benefit from such a framework is demonstrated on a 28nm design, with close SPICE-correlation and verification in a retargeted reliability condition.
UR - http://www.scopus.com/inward/record.url?scp=84926429806&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84926429806&partnerID=8YFLogxK
U2 - 10.1109/ASPDAC.2015.7059029
DO - 10.1109/ASPDAC.2015.7059029
M3 - Conference contribution
AN - SCOPUS:84926429806
T3 - 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
SP - 346
EP - 351
BT - 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
Y2 - 19 January 2015 through 22 January 2015
ER -