A reduced-complexity architecture for LDPC layered decoding schemes

Keyphrases

• Reduced Complexity 100%
• Low-density Parity-check Codes 100%
• Encoding-decoding 100%
• Shuffle-exchange Network 100%
• Layered Decoding 100%
• Irregular Low-density Parity-check Codes 50%
• FPGA Device 50%
• Rate 1 50%
• Xilinx Virtex 50%
• Clock Frequency 50%
• Switching Networks 50%
• Proposed Architecture 50%
• Memory Processing 50%
• Conventional Design 50%
• Virtex-4 50%
• Bit Rate 50%
• Processing Unit 50%
• Decoding Throughput 50%
• Parallel Decoding Scheme 50%
• Memory Bank 50%
• Information Throughput 50%

Computer Science

• Shuffle Network 100%
• Decoding Throughput 50%
• Parallel Block 50%
• low density parity check code 50%
• Processing Unit 50%
• Field Programmable Gate Arrays 50%