A reduced-complexity architecture for LDPC layered decoding schemes

Sangmin Kim, Gerald E. Sobelman, Hanho Lee

Research output: Contribution to journalArticlepeer-review

28 Scopus citations

Abstract

A reduced-complexity low density parity check (LDPC) layered decoding architecture is proposed using an offset permutation scheme in the switch networks. This method requires only one shuffle network, rather than the two shuffle networks which are used in conventional designs. In addition, we use a block parallel decoding scheme by suitably mapping between required memory banks and processing units in order to increase the decoding throughput. The proposed architecture is realized for a 672-bit, rate-1/2 irregular LDPC code on a Xilinx Virtex-4 FPGA device. The design achieves an information throughput of 822 Mb/s at a clock speed of 335 MHz with a maximum of 8 iterations.

Original languageEnglish (US)
Article number5439945
Pages (from-to)1099-1103
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume19
Issue number6
DOIs
StatePublished - Jun 1 2011

Keywords

  • Decoding
  • field-programmable gate array (FPGA)
  • forward error correction
  • low density parity check (LDPC)

Fingerprint Dive into the research topics of 'A reduced-complexity architecture for LDPC layered decoding schemes'. Together they form a unique fingerprint.

Cite this