A Real-Time 17-Scale Object Detection Accelerator with Adaptive 2000-Stage Classification in 65 nm CMOS

Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Luning Wei, Xiaofei He, Yu Cao, Jae Sun Seo

Research output: Contribution to journalArticlepeer-review

5 Scopus citations


Machine learning has become ubiquitous in applications including object detection, image/video classification, and natural language processing. While machine learning algorithms have been successfully used in many practical applications, accurate, fast, and low-power hardware implementations of such algorithms is still a challenging task, especially for mobile systems such as Internet of Things (IoT), autonomous vehicles, and smart drones. This paper presents an energy-efficient programmable ASIC accelerator for object detection. Our ASIC accelerator supports multi-class (e.g., face, traffic sign, car license plate, and pedestrian) that are programmable, many-object (up to 50) in one image with different sizes (17-scale support with 6 down-/11 up-scaling), and high accuracy (AP of 0.87/0.81/0.72/0.76 for FDDB/AFW/BTSD/Caltech datasets). We designed an integral channel detector with 2,000 classifiers for rigid boosted templates, where the number of stages used for classification can be adaptively controlled depending on the content of the search window. This can be implemented with a more modular hardware, compared to support vector machine (SVM) and deformable parts model (DPM) designs. By jointly optimizing the algorithm and the efficient hardware architecture, the prototype chip implemented in 65nm CMOS demonstrates real-Time object detection of 20-50 frames/s with low power consumption of 22.5-181.7 mW (0.54-1.75 nJ/pixel) at 0.58-1.1 V supply.

Original languageEnglish (US)
Article number8741167
Pages (from-to)3843-3853
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number10
StatePublished - Oct 2019
Externally publishedYes

Bibliographical note

Funding Information:
Manuscript received January 6, 2019; revised April 24, 2019; accepted May 30, 2019. Date of publication June 19, 2019; date of current version September 27, 2019. This work was supported in part by NSF under Grant NSF-CCF-1652866, and in part by the Center for Brain-Inspired Computing (C-BRIC), one of six centers in Joint University Microelectronics Program (JUMP), a Semiconductor Research Corporation (SRC) program sponsored by the Defense Advanced Research Projects Agency (DARPA). This paper was recommended by Associate Editor P. K. Meher. (Corresponding author: Minkyu Kim.) M. Kim, A. Mohanty, D. Kadetotad, Y. Cao, and J.-S. Seo are with the School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ 85281 USA (e-mail: mkim152@asu.edu).

Publisher Copyright:
© 2004-2012 IEEE.


  • classification
  • low-power
  • machine learning
  • Object detection
  • real-Time
  • special-purpose accelerator


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