A programmable floating-point cell for systolic signal processing

Ross Smith, Gerald Sobelman, George Luk, Koichi Suda, Jeff Bracken

Research output: Contribution to journalArticlepeer-review


The FPC controller and the AMD Am29325 32-bit floating-point mathematics processor form a two-chip cell designed for one- or two-dimensional systolic arrays which can be used to implement a wide variety of signal processing applications. The FPC controls the Am29325, routes data to and from it, and routes data and control to other cells in the array. Unique architectural features include two interchangeable data memories, an input port which can be used as either a local or global port, and a 32-bit instruction word that allows concurrent use of all cell resources. Additional features include a program memory, two data streams, and three control streams.

Original languageEnglish (US)
Pages (from-to)75-83
Number of pages9
JournalJournal of VLSI Signal Processing
Issue number1
StatePublished - Jan 1993


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