TY - GEN
T1 - A programmable and scalable technique to design spintronic logic circuits based on magnetic tunnel junctions
AU - Patil, Shruti
AU - Lilja, David J
PY - 2011
Y1 - 2011
N2 - Exciting developments are taking place in the field of spintronics, particularly with the advances in the fabrication and characterization of devices such as Magnetic Tunnel Junctions (MTJ). The distinction of spintronic devices from conventional electronic devices makes it challenging to design efficient, scalable and low power logic circuits with MTJs. We propose a programmable and scalable technique to design MTJ-based logic circuits that are capable of implementing any 2-input logic truth table. We present the energy-delay trade-offs of this design with respect to circuit parameters. We also demonstrate that this circuit can be scaled to a 6-input logic function without incurring an increase in the energy consumption.
AB - Exciting developments are taking place in the field of spintronics, particularly with the advances in the fabrication and characterization of devices such as Magnetic Tunnel Junctions (MTJ). The distinction of spintronic devices from conventional electronic devices makes it challenging to design efficient, scalable and low power logic circuits with MTJs. We propose a programmable and scalable technique to design MTJ-based logic circuits that are capable of implementing any 2-input logic truth table. We present the energy-delay trade-offs of this design with respect to circuit parameters. We also demonstrate that this circuit can be scaled to a 6-input logic function without incurring an increase in the energy consumption.
KW - Look-up table
KW - Magnetic tunnel junctions
KW - Programmable spintronics logic
UR - http://www.scopus.com/inward/record.url?scp=79957673706&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79957673706&partnerID=8YFLogxK
U2 - 10.1145/1973009.1973012
DO - 10.1145/1973009.1973012
M3 - Conference contribution
AN - SCOPUS:79957673706
SN - 9781450306676
T3 - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
SP - 7
EP - 12
BT - GLSVLSI'11 - Proceedings of the 2011 Great Lakes Symposium on VLSI
T2 - 21st Great Lakes Symposium on VLSI, GLSVLSI 2011
Y2 - 2 May 2011 through 4 May 2011
ER -