This paper describes a process compensating dynamic (PCD) circuit technique for maintaining the performance benefit of dynamic circuits and reducing the variation in delay and robustness. A variable strength keeper that is optimally programmed based on the die leakage, enables 10% faster performance, 35% reduction in delay variation, and 5× reduction in the number of robustness failing dies, compared to conventional designs. A new leakage current sensor design is also presented that can detect leakage variation and generate the keeper control signals for the PCD technique. Results based on measured leakage data show 1.9-10.2 × higher signal-to-noise ratio (SNR) and reduced sensitivity to supply and p-n skew variations compared to prior leakage sensor designs.
|Original language||English (US)|
|Number of pages||4|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|State||Published - Jun 2006|
Bibliographical noteFunding Information:
Manuscript received August 4, 2005. This work was supported in part by the Semiconductor Research Corporation and by the Intel Ph.D. fellowship. C. Kim is with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA (e-mail: chriskim@umn. edu). K. Roy is with the Department of Electrical and Computer Engineering, Purdue University, Lafayette, IN 47906 USA. S. Hsu, R. Krishnamurthy, and S. Borkar are with Circuit Research, Intel Labs, Hillsboro, OR 97124 USA. Digital Object Identifier 10.1109/TVLSI.2006.878226 Fig. 1. Impact of keeper ratio on dynamic circuit delay and robustness for slow-and fast-corner processes.
Copyright 2008 Elsevier B.V., All rights reserved.
- CMOS digital integrated circuits
- Leakage currents