A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits

Chris H. Kim; Kaushik Roy; Steven Hsu; Ram Krishnamurthy; Shekhar Borkar

doi:10.1109/TVLSI.2006.878226

A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits

Chris H. Kim, Kaushik Roy, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

66 Scopus citations

Abstract

This paper describes a process compensating dynamic (PCD) circuit technique for maintaining the performance benefit of dynamic circuits and reducing the variation in delay and robustness. A variable strength keeper that is optimally programmed based on the die leakage, enables 10% faster performance, 35% reduction in delay variation, and 5× reduction in the number of robustness failing dies, compared to conventional designs. A new leakage current sensor design is also presented that can detect leakage variation and generate the keeper control signals for the PCD technique. Results based on measured leakage data show 1.9-10.2 × higher signal-to-noise ratio (SNR) and reduced sensitivity to supply and p-n skew variations compared to prior leakage sensor designs.

Original language	English (US)
Article number	1661606
Pages (from-to)	646-649
Number of pages	4
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	14
Issue number	6
DOIs	https://doi.org/10.1109/TVLSI.2006.878226
State	Published - Jun 2006

Bibliographical note

Funding Information:
Manuscript received August 4, 2005. This work was supported in part by the Semiconductor Research Corporation and by the Intel Ph.D. fellowship. C. Kim is with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA (e-mail: chriskim@umn. edu). K. Roy is with the Department of Electrical and Computer Engineering, Purdue University, Lafayette, IN 47906 USA. S. Hsu, R. Krishnamurthy, and S. Borkar are with Circuit Research, Intel Labs, Hillsboro, OR 97124 USA. Digital Object Identifier 10.1109/TVLSI.2006.878226 Fig. 1. Impact of keeper ratio on dynamic circuit delay and robustness for slow-and fast-corner processes.

Keywords

CMOS digital integrated circuits
Leakage currents
Microprocessors
VLSI

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10.1109/TVLSI.2006.878226

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abstract = "This paper describes a process compensating dynamic (PCD) circuit technique for maintaining the performance benefit of dynamic circuits and reducing the variation in delay and robustness. A variable strength keeper that is optimally programmed based on the die leakage, enables 10% faster performance, 35% reduction in delay variation, and 5× reduction in the number of robustness failing dies, compared to conventional designs. A new leakage current sensor design is also presented that can detect leakage variation and generate the keeper control signals for the PCD technique. Results based on measured leakage data show 1.9-10.2 × higher signal-to-noise ratio (SNR) and reduced sensitivity to supply and p-n skew variations compared to prior leakage sensor designs.",

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note = "Funding Information: Manuscript received August 4, 2005. This work was supported in part by the Semiconductor Research Corporation and by the Intel Ph.D. fellowship. C. Kim is with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA (e-mail: chriskim@umn. edu). K. Roy is with the Department of Electrical and Computer Engineering, Purdue University, Lafayette, IN 47906 USA. S. Hsu, R. Krishnamurthy, and S. Borkar are with Circuit Research, Intel Labs, Hillsboro, OR 97124 USA. Digital Object Identifier 10.1109/TVLSI.2006.878226 Fig. 1. Impact of keeper ratio on dynamic circuit delay and robustness for slow-and fast-corner processes.",

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A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits

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