A Process Variation Compensating Technique for Sub-90nm Dynamic Circuits

Chris H. Kim; Kaushik Roy; Steven Hsu; Atila Alvandpour; Ram K. Krishnamurthy; Shekhar Borkar

doi:10.1109/VLSIC.2003.1221203

A Process Variation Compensating Technique for Sub-90nm Dynamic Circuits

Chris H. Kim
, Kaushik Roy
, Steven Hsu
, Atila Alvandpour
, Ram K. Krishnamurthy
, Shekhar Borkar

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

35 Scopus citations

Abstract

A process variation compensating technique for sub-90nm dynamic circuits was discussed. It was found that a PCD circuit technique that digitally programs the keeper strength based on die leakage offered 10% higher LBL performance than conventional static keeper scheme. The application of PCD technique to the LBL and global bitline (GBL) of a 2-read, 2-write ported 128-wordx32-bits/word register file in 1.2V, 90 nm CMOS was also elaborated.

Original language	English (US)
Title of host publication	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	205-206
Number of pages	2
ISBN (Print)	4891140348
DOIs	https://doi.org/10.1109/VLSIC.2003.1221203
State	Published - 2003
Event	2003 Symposium on VLSI Circuits - Kyoto, Japan Duration: Jun 12 2003 → Jun 14 2003

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
ISSN (Print)	2158-5601
ISSN (Electronic)	2158-5636

Other

Other	2003 Symposium on VLSI Circuits
Country/Territory	Japan
City	Kyoto
Period	6/12/03 → 6/14/03

Publisher link

10.1109/VLSIC.2003.1221203

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Kim, C. H., Roy, K., Hsu, S., Alvandpour, A., Krishnamurthy, R. K., & Borkar, S. (2003). A Process Variation Compensating Technique for Sub-90nm Dynamic Circuits. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers (pp. 205-206). (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2003.1221203

A Process Variation Compensating Technique for Sub-90nm Dynamic Circuits. / Kim, Chris H.; Roy, Kaushik; Hsu, Steven et al.
IEEE Symposium on VLSI Circuits, Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2003. p. 205-206 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kim, CH, Roy, K, Hsu, S, Alvandpour, A, Krishnamurthy, RK & Borkar, S 2003, A Process Variation Compensating Technique for Sub-90nm Dynamic Circuits. in IEEE Symposium on VLSI Circuits, Digest of Technical Papers. IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Institute of Electrical and Electronics Engineers Inc., pp. 205-206, 2003 Symposium on VLSI Circuits, Kyoto, Japan, 6/12/03. https://doi.org/10.1109/VLSIC.2003.1221203

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abstract = "A process variation compensating technique for sub-90nm dynamic circuits was discussed. It was found that a PCD circuit technique that digitally programs the keeper strength based on die leakage offered 10\% higher LBL performance than conventional static keeper scheme. The application of PCD technique to the LBL and global bitline (GBL) of a 2-read, 2-write ported 128-wordx32-bits/word register file in 1.2V, 90 nm CMOS was also elaborated.",

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language = "English (US)",

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AB - A process variation compensating technique for sub-90nm dynamic circuits was discussed. It was found that a PCD circuit technique that digitally programs the keeper strength based on die leakage offered 10% higher LBL performance than conventional static keeper scheme. The application of PCD technique to the LBL and global bitline (GBL) of a 2-read, 2-write ported 128-wordx32-bits/word register file in 1.2V, 90 nm CMOS was also elaborated.

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A Process Variation Compensating Technique for Sub-90nm Dynamic Circuits

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