Abstract
A process variation compensating technique for sub-90nm dynamic circuits was discussed. It was found that a PCD circuit technique that digitally programs the keeper strength based on die leakage offered 10% higher LBL performance than conventional static keeper scheme. The application of PCD technique to the LBL and global bitline (GBL) of a 2-read, 2-write ported 128-wordx32-bits/word register file in 1.2V, 90 nm CMOS was also elaborated.
| Original language | English (US) |
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| Title of host publication | IEEE Symposium on VLSI Circuits, Digest of Technical Papers |
| Pages | 205-206 |
| Number of pages | 2 |
| State | Published - Oct 1 2003 |
| Event | 2003 Symposium on VLSI Circuits - Kyoto, Japan Duration: Jun 12 2003 → Jun 14 2003 |
Other
| Other | 2003 Symposium on VLSI Circuits |
|---|---|
| Country/Territory | Japan |
| City | Kyoto |
| Period | 6/12/03 → 6/14/03 |