A Process Variation Compensating Technique for Sub-90nm Dynamic Circuits

Chris H. Kim, Kaushik Roy, Steven Hsu, Atila Alvandpour, Ram K. Krishnamurthy, Shekhar Borkar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

35 Scopus citations

Abstract

A process variation compensating technique for sub-90nm dynamic circuits was discussed. It was found that a PCD circuit technique that digitally programs the keeper strength based on die leakage offered 10% higher LBL performance than conventional static keeper scheme. The application of PCD technique to the LBL and global bitline (GBL) of a 2-read, 2-write ported 128-wordx32-bits/word register file in 1.2V, 90 nm CMOS was also elaborated.

Original languageEnglish (US)
Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Pages205-206
Number of pages2
StatePublished - Oct 1 2003
Event2003 Symposium on VLSI Circuits - Kyoto, Japan
Duration: Jun 12 2003Jun 14 2003

Other

Other2003 Symposium on VLSI Circuits
CountryJapan
CityKyoto
Period6/12/036/14/03

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