A predictive distributed congestion metric and its application to technology mapping

Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang

Research output: Contribution to conferencePaperpeer-review

7 Scopus citations

Abstract

Due to increasing design complexity, routing congestion has become a critical problem in VLSI designs. This paper introduces a distributed metric to predict routing congestion for a premapped netlist and applies it to technology mapping that targets area optimization. Our technology mapping algorithm is guided by a probabilistic congestion map for the subject graph to identify the congested regions. Experimental results on the benchmark circuits in a 90nm technology show that congestion-aware mapping results in a reduction of 37%, on an average, in track overflows as compared to conventional technology mapping.

Original languageEnglish (US)
Pages210-217
Number of pages8
DOIs
StatePublished - 2004
EventProceedings of the International Symposium on Physical Design, ISPD 2004 - Phoenix, AZ, United States
Duration: Apr 18 2004Apr 21 2004

Other

OtherProceedings of the International Symposium on Physical Design, ISPD 2004
CountryUnited States
CityPhoenix, AZ
Period4/18/044/21/04

Keywords

  • Congestion prediction
  • Technology mapping

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