A practical methodology for early buffer and wire resource allocation

Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul G. Villarrubia

Research output: Contribution to journalArticlepeer-review

59 Scopus citations

Abstract

The dominating contribution of interconnect to system performance has made it critical to plan for buffer and wiring resources in the layout. Both buffers and wires must be considered, since wire routes determine buffer requirements and buffer locations constrain wire routes. In contrast to recent buffer block planning approaches, our design methodology distributes buffer sites throughout the layout. A tile graph is used to abstract the buffer planning problem while also addressing wire planning. We present a four-stage heuristic called RABID for resource allocation and experimentally verify its effectiveness.

Original languageEnglish (US)
Pages (from-to)189-194
Number of pages6
JournalProceedings - Design Automation Conference
DOIs
StatePublished - Jan 1 2001

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