A power and cluster-aware technology mapping and clustering scheme for dual-VT FPGAs

In this paper, we present a technology mapping and clustering tool for leakage power reduction in FPGAs with programmable, dual-VT logic blocks. The use of Reverse Back Bias (RBB) circuit techniques is recognized as one of the more promising strategies in mitigating leakage power, a critical problem in circuits deploying deep submicron process technologies. FPGAs with the ability to adjust fabric VT through RBB offer the potential of reducing leakage power with minimal or no sacrifice to circuit speed. Today, Altera's Stratix line of FPGAs deploy a similar strategy, but with optimizations limited to the post-P&R stage. We present a novel two-stage technology mapping (RBBMap) and logic block packing (RBBPack) tool that is free from clustering constraints limiting the post-P&R method, and moves RBB optimizations upwards to the technology mapping level. Using the baseline technology mapping tool Emap, our tools generate an average of 70.95% savings in logic block leakage power and 28.30% savings in total energy consumption.