A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited

Jian Ping Wang; Sachin S. Sapatnekar; Chris H. Kim; Paul Crowell; Steve Koester; Supriyo Datta; Kaushik Roy; Anand Raghunathan; X. Sharon Hu; Michael Niemier; Azad Naeemi; Chia Ling Chien; Caroline Ross; Roland Kawakami

doi:10.1145/3061639.3072942

A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited

Jian Ping Wang, Sachin S. Sapatnekar, Chris H. Kim, Paul Crowell, Steve Koester, Supriyo Datta, Kaushik Roy, Anand Raghunathan, X. Sharon Hu, Michael Niemier, Azad Naeemi, Chia Ling Chien, Caroline Ross, Roland Kawakami

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

22 Scopus citations

Abstract

Many key technologies of our society, including so-called artificial intelligence (AI) and big data, have been enabled by the invention of transistor and its ever-decreasing size and ever-increasing integration at a large scale. However, conventional technologies are confronted with a clear scaling limit. Many recently proposed advanced transistor concepts are also facing an uphill battle in the lab because of necessary performance tradeoffs and limited scaling potential. We argue for a new pathway that could enable exponential scaling for multiple generations. This pathway involves layering multiple technologies that enable new functions beyond those available from conventional and newly proposed transistors. The key principles for this new pathway have been demonstrated through an interdisciplinary team effort at C-SPIN (a STARnet center), where systems designers, device builders, materials scientists and physicists have all worked under one umbrella to overcome key technology barriers. This paper reviews several successful outcomes from this effort on topics such as the spin memory, logic-in-memory, cognitive computing, stochastic and probabilistic computing and reconfigurable information processing.

Original language	English (US)
Title of host publication	Proceedings of the 54th Annual Design Automation Conference 2017, DAC 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781450349277
DOIs	https://doi.org/10.1145/3061639.3072942
State	Published - Jun 18 2017
Event	54th Annual Design Automation Conference, DAC 2017 - Austin, United States Duration: Jun 18 2017 → Jun 22 2017

Publication series

Name	Proceedings - Design Automation Conference
Volume	Part 128280
ISSN (Print)	0738-100X

Other

Other	54th Annual Design Automation Conference, DAC 2017
Country/Territory	United States
City	Austin
Period	6/18/17 → 6/22/17

Bibliographical note

Funding Information:
This work was supported by C-SPIN, one of six centers of STARnet, a Semiconductor Research Corporation program, sponsored by MARCO and DARPA.

Keywords

Spintronics
beyond-CMOS
logic-in-memory
neuromorphic computing
nonvolatile computing
post-CMOS
probabilistic computing
spin logic
spin memory
stochastic computing

Publisher link

10.1145/3061639.3072942

Find It

Find It at U of M Libraries

Cite this

Wang, J. P., Sapatnekar, S. S., Kim, C. H., Crowell, P., Koester, S., Datta, S., Roy, K., Raghunathan, A., Hu, X. S., Niemier, M., Naeemi, A., Chien, C. L., Ross, C., & Kawakami, R. (2017). A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited. In Proceedings of the 54th Annual Design Automation Conference 2017, DAC 2017 Article 16 (Proceedings - Design Automation Conference; Vol. Part 128280). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/3061639.3072942

A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited. / Wang, Jian Ping ; Sapatnekar, Sachin S.; Kim, Chris H. et al.
Proceedings of the 54th Annual Design Automation Conference 2017, DAC 2017. Institute of Electrical and Electronics Engineers Inc., 2017. 16 (Proceedings - Design Automation Conference; Vol. Part 128280).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Wang, JP , Sapatnekar, SS , Kim, CH , Crowell, P , Koester, S, Datta, S, Roy, K, Raghunathan, A, Hu, XS, Niemier, M, Naeemi, A, Chien, CL, Ross, C & Kawakami, R 2017, A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited. in Proceedings of the 54th Annual Design Automation Conference 2017, DAC 2017., 16, Proceedings - Design Automation Conference, vol. Part 128280, Institute of Electrical and Electronics Engineers Inc., 54th Annual Design Automation Conference, DAC 2017, Austin, United States, 6/18/17. https://doi.org/10.1145/3061639.3072942

@inproceedings{9abdc1035fb545febf0e3f59bfca54dd,

title = "A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited",

abstract = "Many key technologies of our society, including so-called artificial intelligence (AI) and big data, have been enabled by the invention of transistor and its ever-decreasing size and ever-increasing integration at a large scale. However, conventional technologies are confronted with a clear scaling limit. Many recently proposed advanced transistor concepts are also facing an uphill battle in the lab because of necessary performance tradeoffs and limited scaling potential. We argue for a new pathway that could enable exponential scaling for multiple generations. This pathway involves layering multiple technologies that enable new functions beyond those available from conventional and newly proposed transistors. The key principles for this new pathway have been demonstrated through an interdisciplinary team effort at C-SPIN (a STARnet center), where systems designers, device builders, materials scientists and physicists have all worked under one umbrella to overcome key technology barriers. This paper reviews several successful outcomes from this effort on topics such as the spin memory, logic-in-memory, cognitive computing, stochastic and probabilistic computing and reconfigurable information processing.",

keywords = "Spintronics, beyond-CMOS, logic-in-memory, neuromorphic computing, nonvolatile computing, post-CMOS, probabilistic computing, spin logic, spin memory, stochastic computing",

author = "Wang, {Jian Ping} and Sapatnekar, {Sachin S.} and Kim, {Chris H.} and Paul Crowell and Steve Koester and Supriyo Datta and Kaushik Roy and Anand Raghunathan and Hu, {X. Sharon} and Michael Niemier and Azad Naeemi and Chien, {Chia Ling} and Caroline Ross and Roland Kawakami",

note = "Funding Information: This work was supported by C-SPIN, one of six centers of STARnet, a Semiconductor Research Corporation program, sponsored by MARCO and DARPA.; 54th Annual Design Automation Conference, DAC 2017 ; Conference date: 18-06-2017 Through 22-06-2017",

year = "2017",

month = jun,

day = "18",

doi = "10.1145/3061639.3072942",

language = "English (US)",

series = "Proceedings - Design Automation Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "Proceedings of the 54th Annual Design Automation Conference 2017, DAC 2017",

}

TY - GEN

T1 - A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era

T2 - 54th Annual Design Automation Conference, DAC 2017

AU - Wang, Jian Ping

AU - Sapatnekar, Sachin S.

AU - Kim, Chris H.

AU - Crowell, Paul

AU - Koester, Steve

AU - Datta, Supriyo

AU - Roy, Kaushik

AU - Raghunathan, Anand

AU - Hu, X. Sharon

AU - Niemier, Michael

AU - Naeemi, Azad

AU - Chien, Chia Ling

AU - Ross, Caroline

AU - Kawakami, Roland

N1 - Funding Information: This work was supported by C-SPIN, one of six centers of STARnet, a Semiconductor Research Corporation program, sponsored by MARCO and DARPA.

PY - 2017/6/18

Y1 - 2017/6/18

N2 - Many key technologies of our society, including so-called artificial intelligence (AI) and big data, have been enabled by the invention of transistor and its ever-decreasing size and ever-increasing integration at a large scale. However, conventional technologies are confronted with a clear scaling limit. Many recently proposed advanced transistor concepts are also facing an uphill battle in the lab because of necessary performance tradeoffs and limited scaling potential. We argue for a new pathway that could enable exponential scaling for multiple generations. This pathway involves layering multiple technologies that enable new functions beyond those available from conventional and newly proposed transistors. The key principles for this new pathway have been demonstrated through an interdisciplinary team effort at C-SPIN (a STARnet center), where systems designers, device builders, materials scientists and physicists have all worked under one umbrella to overcome key technology barriers. This paper reviews several successful outcomes from this effort on topics such as the spin memory, logic-in-memory, cognitive computing, stochastic and probabilistic computing and reconfigurable information processing.

AB - Many key technologies of our society, including so-called artificial intelligence (AI) and big data, have been enabled by the invention of transistor and its ever-decreasing size and ever-increasing integration at a large scale. However, conventional technologies are confronted with a clear scaling limit. Many recently proposed advanced transistor concepts are also facing an uphill battle in the lab because of necessary performance tradeoffs and limited scaling potential. We argue for a new pathway that could enable exponential scaling for multiple generations. This pathway involves layering multiple technologies that enable new functions beyond those available from conventional and newly proposed transistors. The key principles for this new pathway have been demonstrated through an interdisciplinary team effort at C-SPIN (a STARnet center), where systems designers, device builders, materials scientists and physicists have all worked under one umbrella to overcome key technology barriers. This paper reviews several successful outcomes from this effort on topics such as the spin memory, logic-in-memory, cognitive computing, stochastic and probabilistic computing and reconfigurable information processing.

KW - Spintronics

KW - beyond-CMOS

KW - logic-in-memory

KW - neuromorphic computing

KW - nonvolatile computing

KW - post-CMOS

KW - probabilistic computing

KW - spin logic

KW - spin memory

KW - stochastic computing

UR - http://www.scopus.com/inward/record.url?scp=85023639883&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85023639883&partnerID=8YFLogxK

U2 - 10.1145/3061639.3072942

DO - 10.1145/3061639.3072942

M3 - Conference contribution

AN - SCOPUS:85023639883

T3 - Proceedings - Design Automation Conference

BT - Proceedings of the 54th Annual Design Automation Conference 2017, DAC 2017

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 18 June 2017 through 22 June 2017

ER -

A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited

Abstract

Publication series

Other

Bibliographical note

Keywords

Publisher link

Find It

Other files and links

Fingerprint

Cite this