A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited

Jian Ping Wang, Sachin S. Sapatnekar, Chris H. Kim, Paul Crowell, Steve Koester, Supriyo Datta, Kaushik Roy, Anand Raghunathan, X. Sharon Hu, Michael Niemier, Azad Naeemi, Chia Ling Chien, Caroline Ross, Roland Kawakami

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

Many key technologies of our society, including so-called artificial intelligence (AI) and big data, have been enabled by the invention of transistor and its ever-decreasing size and ever-increasing integration at a large scale. However, conventional technologies are confronted with a clear scaling limit. Many recently proposed advanced transistor concepts are also facing an uphill battle in the lab because of necessary performance tradeoffs and limited scaling potential. We argue for a new pathway that could enable exponential scaling for multiple generations. This pathway involves layering multiple technologies that enable new functions beyond those available from conventional and newly proposed transistors. The key principles for this new pathway have been demonstrated through an interdisciplinary team effort at C-SPIN (a STARnet center), where systems designers, device builders, materials scientists and physicists have all worked under one umbrella to overcome key technology barriers. This paper reviews several successful outcomes from this effort on topics such as the spin memory, logic-in-memory, cognitive computing, stochastic and probabilistic computing and reconfigurable information processing.

Original languageEnglish (US)
Title of host publicationProceedings of the 54th Annual Design Automation Conference 2017, DAC 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781450349277
DOIs
StatePublished - Jun 18 2017
Event54th Annual Design Automation Conference, DAC 2017 - Austin, United States
Duration: Jun 18 2017Jun 22 2017

Publication series

NameProceedings - Design Automation Conference
VolumePart 128280
ISSN (Print)0738-100X

Other

Other54th Annual Design Automation Conference, DAC 2017
CountryUnited States
CityAustin
Period6/18/176/22/17

Keywords

  • Spintronics
  • beyond-CMOS
  • logic-in-memory
  • neuromorphic computing
  • nonvolatile computing
  • post-CMOS
  • probabilistic computing
  • spin logic
  • spin memory
  • stochastic computing

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    Wang, J. P., Sapatnekar, S. S., Kim, C. H., Crowell, P., Koester, S., Datta, S., Roy, K., Raghunathan, A., Hu, X. S., Niemier, M., Naeemi, A., Chien, C. L., Ross, C., & Kawakami, R. (2017). A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited. In Proceedings of the 54th Annual Design Automation Conference 2017, DAC 2017 [16] (Proceedings - Design Automation Conference; Vol. Part 128280). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/3061639.3072942