TY - GEN
T1 - A novel multiply multiple accumulator component for low power PDSP design
AU - Sundararajan, Vijay
AU - Parhi, Keshab K.
PY - 2000/1/1
Y1 - 2000/1/1
N2 - This paper presents a novel programmable digital signal processor (PDSP) component called the multiply multiple accumulator (MMAC). The MMAC differs from a standard multiply accumulator (MAC) in that it has k addressable accumulators rather than 1 in the case of the MAC. It is demonstrated that this feature of the MMAC can provide for low power scheduling of FIR filter operations. Typically, the number of read accesses to associated memories can come down, asymptotically, by a factor of k. The switching activity of associated multipliers also comes down by a factor of k.
AB - This paper presents a novel programmable digital signal processor (PDSP) component called the multiply multiple accumulator (MMAC). The MMAC differs from a standard multiply accumulator (MAC) in that it has k addressable accumulators rather than 1 in the case of the MAC. It is demonstrated that this feature of the MMAC can provide for low power scheduling of FIR filter operations. Typically, the number of read accesses to associated memories can come down, asymptotically, by a factor of k. The switching activity of associated multipliers also comes down by a factor of k.
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U2 - 10.1109/ICASSP.2000.860092
DO - 10.1109/ICASSP.2000.860092
M3 - Conference contribution
AN - SCOPUS:0033693952
T3 - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
SP - 3247
EP - 3250
BT - Design and Implementation of Signal Processing SystemNeural Networks for Signal Processing Signal Processing EducationOther Emerging Applications of Signal ProcessingSpecial Sessions
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 25th IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2000
Y2 - 5 June 2000 through 9 June 2000
ER -