A novel multiply multiple accumulator component for low power PDSP design

Vijay Sundararajan, Keshab K. Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

This paper presents a novel programmable digital signal processor (PDSP) component called the multiply multiple accumulator (MMAC). The MMAC differs from a standard multiply accumulator (MAC) in that it has k addressable accumulators rather than 1 in the case of the MAC. It is demonstrated that this feature of the MMAC can provide for low power scheduling of FIR filter operations. Typically, the number of read accesses to associated memories can come down, asymptotically, by a factor of k. The switching activity of associated multipliers also comes down by a factor of k.

Original languageEnglish (US)
Title of host publicationDesign and Implementation of Signal Processing SystemNeural Networks for Signal Processing Signal Processing EducationOther Emerging Applications of Signal ProcessingSpecial Sessions
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages3247-3250
Number of pages4
ISBN (Electronic)0780362934
DOIs
StatePublished - Jan 1 2000
Event25th IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2000 - Istanbul, Turkey
Duration: Jun 5 2000Jun 9 2000

Publication series

NameICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Volume6
ISSN (Print)1520-6149

Other

Other25th IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2000
Country/TerritoryTurkey
CityIstanbul
Period6/5/006/9/00

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