Abstract
In this paper, a novel algorithm to reduce the intermediate buffer size of a Solid State Drive (SSD) controller has been proposed. The algorithm implements compression and encryption to reduce the stored data and secure it. The cyclic operation of compression and encryption reduces the intermediate buffer size substantially compared to serial operation. The algorithm has been optimized and tested for different standards of Xtensa processor and the best suitable standard has been reported in terms of processor cycles.
Original language | English (US) |
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Title of host publication | Proceedings of 9th International Conference on Electrical and Computer Engineering, ICECE 2016 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 234-237 |
Number of pages | 4 |
ISBN (Electronic) | 9781509029631 |
DOIs | |
State | Published - Feb 13 2017 |
Externally published | Yes |
Event | 9th International Conference on Electrical and Computer Engineering, ICECE 2016 - Dhaka, Bangladesh Duration: Dec 20 2016 → Dec 22 2016 |
Publication series
Name | Proceedings of 9th International Conference on Electrical and Computer Engineering, ICECE 2016 |
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Conference
Conference | 9th International Conference on Electrical and Computer Engineering, ICECE 2016 |
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Country/Territory | Bangladesh |
City | Dhaka |
Period | 12/20/16 → 12/22/16 |
Bibliographical note
Publisher Copyright:© 2016 IEEE.
Keywords
- AES-128
- LZ77
- Minimum clock rate
- Optimization
- Processor cycles