A novel low buffered optimized solid state drive controller

Ratul Das, Baishakhi Rani Biswas, A. B.M.Harun Ur Rashid, M. A. Abedin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, a novel algorithm to reduce the intermediate buffer size of a Solid State Drive (SSD) controller has been proposed. The algorithm implements compression and encryption to reduce the stored data and secure it. The cyclic operation of compression and encryption reduces the intermediate buffer size substantially compared to serial operation. The algorithm has been optimized and tested for different standards of Xtensa processor and the best suitable standard has been reported in terms of processor cycles.

Original languageEnglish (US)
Title of host publicationProceedings of 9th International Conference on Electrical and Computer Engineering, ICECE 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages234-237
Number of pages4
ISBN (Electronic)9781509029631
DOIs
StatePublished - Feb 13 2017
Externally publishedYes
Event9th International Conference on Electrical and Computer Engineering, ICECE 2016 - Dhaka, Bangladesh
Duration: Dec 20 2016Dec 22 2016

Publication series

NameProceedings of 9th International Conference on Electrical and Computer Engineering, ICECE 2016

Conference

Conference9th International Conference on Electrical and Computer Engineering, ICECE 2016
Country/TerritoryBangladesh
CityDhaka
Period12/20/1612/22/16

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

Keywords

  • AES-128
  • LZ77
  • Minimum clock rate
  • Optimization
  • Processor cycles

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