One-dimensional rank order filters are non-linear filters which choose an output based on its rank within a onedimensional window of sample inputs determined by sorting the inputs. Several extensions to rank order filtering include recursive rank order filtering, two-stage rank order filtering, stack filtering, and two-dimensional rank order filtering. Two classes of VLSI architectures are commonly used for rank order filtering. The first class stores the inputs within the sample window in a shift register and employs sorting networks to completely sort the window of inputs when a new sample arrives. The second class called running order sorters utilizes the overlapping windows between consecutive outputs to efficiently maintain a sorted list of the inputs within the window. Although the class two architectures are computationally more efficient than the class one architectures, they are difficult both to pipeline and to apply to the rank order filter extensions. A new VLSI architecture for rank order filtering is presented in this paper. This architecture is an addition to the class two rank order filter architectures and can be pipelined and applied to the extensions to rank order filtering.
|Original language||English (US)|
|Title of host publication||1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||4|
|State||Published - 1992|
|Event||1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 - San Diego, United States|
Duration: May 10 1992 → May 13 1992
|Name||Proceedings - IEEE International Symposium on Circuits and Systems|
|Conference||1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992|
|Period||5/10/92 → 5/13/92|
Bibliographical noteFunding Information:
This research wss supported in parts by an AT&T graduate fellowship and the Office of Naval Research under contract number N00014-91-J-1008.
© 1992 IEEE.