A new approach to the use of satisfiability in false path detection

Felipe S. Marques, Renato P. Ribas, Sachin S Sapatnekar, André I. Reis

Research output: Contribution to conferencePaper

6 Scopus citations

Abstract

This paper presents a novel method for false path detection using satisfiability. It is based on circuit node properties that are related to non-testable stuck-at faults as well as to false path detection. When compared to traditional satisfiability methods that generate sat instances associated to paths, the proposed method is more efficient. This efficiency derives from the fact that most digital circuits have a number of nodes that is smaller than the number of paths.

Original languageEnglish (US)
Pages308-311
Number of pages4
StatePublished - Dec 29 2005
Event2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05 - Chicago, IL, United States
Duration: Apr 17 2005Apr 19 2005

Other

Other2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05
CountryUnited States
CityChicago, IL
Period4/17/054/19/05

Keywords

  • False Paths
  • Satisfiability
  • Unateness

Fingerprint Dive into the research topics of 'A new approach to the use of satisfiability in false path detection'. Together they form a unique fingerprint.

  • Cite this

    Marques, F. S., Ribas, R. P., Sapatnekar, S. S., & Reis, A. I. (2005). A new approach to the use of satisfiability in false path detection. 308-311. Paper presented at 2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05, Chicago, IL, United States.