A new analytical delay and noise model for on-chip RLC interconnect

Y. Cao; X. Huang; D. Sylvester; N. Chang; C. Hu

A new analytical delay and noise model for on-chip RLC interconnect

Y. Cao, X. Huang, D. Sylvester, N. Chang, C. Hu

Research output: Contribution to journal › Conference article › peer-review

Abstract

In this paper, we develop a 2^nd order distributed RLC waveform model that captures both delay and overshoot effects more accurately than previous 1^st order models. We then present a new approach to decoupling a set of coupled RLC lines by examining current return paths. Noise and delay results from this technique match SPICE for a wide range of input parameters.

Original language	English (US)
Pages (from-to)	823-826
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
State	Published - 2000
Externally published	Yes
Event	2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States Duration: Dec 10 2000 → Dec 13 2000

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@article{0e61b8d8c2194292bdd68db496a641e5,

title = "A new analytical delay and noise model for on-chip RLC interconnect",

abstract = "In this paper, we develop a 2nd order distributed RLC waveform model that captures both delay and overshoot effects more accurately than previous 1st order models. We then present a new approach to decoupling a set of coupled RLC lines by examining current return paths. Noise and delay results from this technique match SPICE for a wide range of input parameters.",

author = "Y. Cao and X. Huang and D. Sylvester and N. Chang and C. Hu",

year = "2000",

language = "English (US)",

pages = "823--826",

journal = "Technical Digest - International Electron Devices Meeting",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2000 IEEE International Electron Devices Meeting ; Conference date: 10-12-2000 Through 13-12-2000",

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TY - JOUR

T1 - A new analytical delay and noise model for on-chip RLC interconnect

AU - Cao, Y.

AU - Huang, X.

AU - Sylvester, D.

AU - Chang, N.

AU - Hu, C.

PY - 2000

Y1 - 2000

N2 - In this paper, we develop a 2nd order distributed RLC waveform model that captures both delay and overshoot effects more accurately than previous 1st order models. We then present a new approach to decoupling a set of coupled RLC lines by examining current return paths. Noise and delay results from this technique match SPICE for a wide range of input parameters.

AB - In this paper, we develop a 2nd order distributed RLC waveform model that captures both delay and overshoot effects more accurately than previous 1st order models. We then present a new approach to decoupling a set of coupled RLC lines by examining current return paths. Noise and delay results from this technique match SPICE for a wide range of input parameters.

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UR - http://www.scopus.com/inward/citedby.url?scp=0034449490&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0034449490

SN - 0163-1918

SP - 823

EP - 826

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

T2 - 2000 IEEE International Electron Devices Meeting

Y2 - 10 December 2000 through 13 December 2000

ER -

A new analytical delay and noise model for on-chip RLC interconnect

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