A multichannel integrated circuit for neural spike detection based on EC-PC threshold estimation

Tong Wu, Zhi Yang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

In extracellular neural recording experiments, spike detection is an important step for information decoding of neuronal activities. An ASIC implementation of detection algorithms can provide substantial data-rate reduction and facilitate wireless operations. In this paper, we present a 16-channel neural spike detection ASIC. The chip takes raw data as inputs, and outputs three data streams simultaneously: field potentials down sampled at 1.25 KHz, band-pass filtered neural data, and spiking probability maps sampled at 40 KHz. The functionality and the performance of the chip have been verified in both in-vivo and benchtop experiments. Fabricated in a 0.13 μm CMOS process, the chip has a peak power dissipation of 85 μW per channel and achieves a data-rate reduction of 98.44%.

Original languageEnglish (US)
Title of host publication2013 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBC 2013
Pages779-782
Number of pages4
DOIs
StatePublished - Oct 31 2013
Event2013 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBC 2013 - Osaka, Japan
Duration: Jul 3 2013Jul 7 2013

Publication series

NameProceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBS
ISSN (Print)1557-170X

Other

Other2013 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBC 2013
CountryJapan
CityOsaka
Period7/3/137/7/13

Fingerprint Dive into the research topics of 'A multichannel integrated circuit for neural spike detection based on EC-PC threshold estimation'. Together they form a unique fingerprint.

Cite this