A multi-phase VCO quantizer based adaptive digital LDO in 65nm CMOS technology

Somnath Kundu, Chris H. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

A digital low-dropout (DLDO) voltage regulator circuit is proposed utilizing a multi-phase VCO based time quantizer. This high-resolution quantizer requires much lower sampling clock frequency compared to the previously proposed 1-bit comparator based architectures and thereby ensures stability over a wide operating condition, while reducing the dynamic power consumption at the same time. The DLDO operates at an input voltage range of 0.6V to 1.2V and delivers a maximum 115mA current with a 50mV dropout, simulated in a 65nm LP CMOS technology. A dynamically adaptive sampling clock can reduce the output voltage droop by 40-60% and provides 3.5-6.5 times faster settling compared to a baseline DLDO design that uses a fixed sampling clock frequency. The FOM calculated at 0.9V output is 0.53ps. The maximum current efficiency is 99.3%.

Original languageEnglish (US)
Title of host publicationIEEE International Symposium on Circuits and Systems
Subtitle of host publicationFrom Dreams to Innovation, ISCAS 2017 - Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467368520
DOIs
StatePublished - Sep 25 2017
Event50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, United States
Duration: May 28 2017May 31 2017

Other

Other50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
Country/TerritoryUnited States
CityBaltimore
Period5/28/175/31/17

Keywords

  • adaptive sampling
  • digital low dropout regulator
  • time-based quantizer
  • voltage-controlled oscillator

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