A fault preprocessing procedure that determines the detectability of transistor faults is presented, and examples are given for static and dynamic CMOS logic. The fault simulation procedure is presented for both logic and IDDQ testing. Simulation results for typical circuits are also presented.
|Original language||English (US)|
|Number of pages||7|
|Journal||Digest of Papers - International Test Conference|
|State||Published - Jan 1 1992|