Abstract
We present an early-stage global wire-design methodology that simultaneously considers the performance needs for both signal lines and power grids under congestion considerations. An iterative procedure is employed in which the global routing is performed according to a congestion map that includes the resource utilization of the power grid, followed by a step in which the power grid is adjusted to relax the congestion in crowded regions. This adjustment is in the form of wire removal in noncritical regions, followed by a wire-sizing step that overcomes the voltage noise after wire removal and a wire-width resizing that meets the maximum current-density constraint. Experimental results show that the overall mutability can be significantly improved while the power-grid noise is maintained within both the voltage-drop and current-density constraints.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 1614-1624 |
| Number of pages | 11 |
| Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
| Volume | 23 |
| Issue number | 12 |
| DOIs | |
| State | Published - Dec 2004 |
Bibliographical note
Funding Information:Manuscript received March 29, 2002; revised October 31, 2003. This work was supported in part by the National Science Foundation under Award CCR-0098117 and by the Semiconductor Research Corporation under Contract 99-TJ-714. This paper was recommended by Associate Editor T. Yoshimura. H. Su and S. R. Nassif are with the IBM Corporation, Austin, TX 78758 USA (e-mail: haihua@us.ibm.com; nassif@us.ibm.com). J. Hu is with the Electrical Engineering Department, Texas A&M University, College Station, TX 77843 USA (e-mail: jianghu@ee.tamu.edu). S. S. Sapatnekar is with the Electrical and Computer Engineering Department, University of Minnesota, Minneapolis, MN 55455 USA (e-mail: sachin@ece.umn.edu). Digital Object Identifier 10.1109/TCAD.2004.837728
Keywords
- Circuit optimization
- Design automation
- Power distribution
- Routing
- Sensitivity