A method for measuring and alleviating clock-jitter in continuous-time delta-sigma modulators

Jiang Yanfeng, Zhang Xiaobo, Yang Bing

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Continuous-time Delta-Sigma modulators are able to operate at higher frequencies than their discrete-time counterparts. However, they suffer more severely from non-idealities such as clock jitter. A method for measuring this clock jitter has been proposed. Moreover, the effect of the non-ideality are explained and a continuous-time to discrete-time conversion method is presented in order to aid in the analysis of this effect. The SC-R feedback circuit has been presented here to help eliminate clock jitter noise.

Original languageEnglish (US)
Title of host publicationProceedings of 2009 7th Asian Control Conference, ASCC 2009
Pages567-570
Number of pages4
StatePublished - Dec 11 2009
Event2009 7th Asian Control Conference, ASCC 2009 - Hong Kong, China
Duration: Aug 27 2009Aug 29 2009

Other

Other2009 7th Asian Control Conference, ASCC 2009
CountryChina
CityHong Kong
Period8/27/098/29/09

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