TY - JOUR
T1 - A method for correcting the functionality of a wire-pipelined circuit
AU - Nookala, Vidyasagar
AU - Sapatnekar, Sachin S
PY - 2004
Y1 - 2004
N2 - As across-chip interconnect delays can exceed a clock cycle, wire pipelining becomes essential in high performance designs. Although it allows higher clock frequencies, it may change the microarchitecture altogether because of the arbitrary increase in the latencies of the paths and cycles of the circuit. This paper proposes a method to regain the functionality of a wire-pipelined circuit. In this approach, increased cycle latencies are compensated by slowing down the issue rate of the inputs. Our method finds the optimal value of the slowdown required for a circuit as it directly affects the throughput of the circuit. We also incorporate area minimization in our formulation to minimize the number of extra flip-flops added to the circuit. The formulation is tested on circuits derived from ISCAS benchmarks and the results suggest that wire pipelining increases the overall throughput in most of the cases.
AB - As across-chip interconnect delays can exceed a clock cycle, wire pipelining becomes essential in high performance designs. Although it allows higher clock frequencies, it may change the microarchitecture altogether because of the arbitrary increase in the latencies of the paths and cycles of the circuit. This paper proposes a method to regain the functionality of a wire-pipelined circuit. In this approach, increased cycle latencies are compensated by slowing down the issue rate of the inputs. Our method finds the optimal value of the slowdown required for a circuit as it directly affects the throughput of the circuit. We also incorporate area minimization in our formulation to minimize the number of extra flip-flops added to the circuit. The formulation is tested on circuits derived from ISCAS benchmarks and the results suggest that wire pipelining increases the overall throughput in most of the cases.
KW - Synchronous design
KW - Wire pipelining
UR - http://www.scopus.com/inward/record.url?scp=4444361440&partnerID=8YFLogxK
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U2 - 10.1145/996566.996724
DO - 10.1145/996566.996724
M3 - Conference article
AN - SCOPUS:4444361440
SP - 570
EP - 575
JO - Proceedings - Design Automation Conference
JF - Proceedings - Design Automation Conference
SN - 0738-100X
T2 - Proceedings of the 41st Design Automation Conference
Y2 - 7 June 2004 through 11 June 2004
ER -