A memory optimized mersenne-twister random number generator

Random number generators (RNGs) are an integral component of numerous stochastic simulation methods, with applications in diverse scientific disciplines. Recently, stochastic simulation methods are being increasingly implemented on FPGAs for improved performance. Consequently, efficient RNG implementations are essential to successfully realize stochastic simulation methods on FPGAs. We present a memory optimized architecture of the prominent Mersenne-Twister RNG (MT-RNG) for efficient implementation on FPGAs. Our approach leverages the different memory constructs available on an FPGA device to reduce the memory requirements of our architecture by upto 50% over existing designs in published literature. Furthermore, we perform an out-of-order computation of random numbers to reduce the hardware area of our MT-RNG implementation, and compare the hardware metrics of our proposed architecture with the existing implementations on different FPGA platforms.