A low-power VLSI implementation for variable block size motion estimation in H.264/AVC

Peng Li, Hua Tang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

Variable block size motion estimation (VBSME) is becoming the new coding technique in H.264/AVC. This paper presents a low-power VLSI implementation for fullsearch VBSME. Compared to existing hardware architectures and implementations for VBSME, the proposed design employs a fast full-search block matching algorithm to reduce power consumption, while preserving the optimal solution and the throughput. The proposed architecture has been implemented and tested in Xilinx XtremeDSP Video Starter Kit Spartan-3ADSP 3400A Edition, and also verified using standard cell approach in UMC 0.18μm CMOS technology. Compared to other VBSME designs that give optimal solutions of Motion Vectors (MV), the proposed design can save power consumption by more than 56%.

Original languageEnglish (US)
Title of host publicationISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
Subtitle of host publicationNano-Bio Circuit Fabrics and Systems
Pages2972-2975
Number of pages4
DOIs
StatePublished - Aug 31 2010
Event2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France
Duration: May 30 2010Jun 2 2010

Publication series

NameISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Other

Other2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
CountryFrance
CityParis
Period5/30/106/2/10

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