A low-power VLSI implementation for variable block size motion estimation in H.264/AVC

Peng Li; Hua Tang

doi:10.1109/ISCAS.2010.5538025

A low-power VLSI implementation for variable block size motion estimation in H.264/AVC

Peng Li, Hua Tang

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Scopus citations

Abstract

Variable block size motion estimation (VBSME) is becoming the new coding technique in H.264/AVC. This paper presents a low-power VLSI implementation for fullsearch VBSME. Compared to existing hardware architectures and implementations for VBSME, the proposed design employs a fast full-search block matching algorithm to reduce power consumption, while preserving the optimal solution and the throughput. The proposed architecture has been implemented and tested in Xilinx XtremeDSP Video Starter Kit Spartan-3ADSP 3400A Edition, and also verified using standard cell approach in UMC 0.18μm CMOS technology. Compared to other VBSME designs that give optimal solutions of Motion Vectors (MV), the proposed design can save power consumption by more than 56%.

Original language	English (US)
Title of host publication	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
Subtitle of host publication	Nano-Bio Circuit Fabrics and Systems
Pages	2972-2975
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2010.5538025
State	Published - Aug 31 2010
Event	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France Duration: May 30 2010 → Jun 2 2010

Publication series

Name	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Other

Other	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
Country/Territory	France
City	Paris
Period	5/30/10 → 6/2/10

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10.1109/ISCAS.2010.5538025

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Li, P., & Tang, H. (2010). A low-power VLSI implementation for variable block size motion estimation in H.264/AVC. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (pp. 2972-2975). Article 5538025 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). https://doi.org/10.1109/ISCAS.2010.5538025

A low-power VLSI implementation for variable block size motion estimation in H.264/AVC. / Li, Peng; Tang, Hua.
ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 2972-2975 5538025 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Li, P & Tang, H 2010, A low-power VLSI implementation for variable block size motion estimation in H.264/AVC. in ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems., 5538025, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, pp. 2972-2975, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, Paris, France, 5/30/10. https://doi.org/10.1109/ISCAS.2010.5538025

Li P, Tang H. A low-power VLSI implementation for variable block size motion estimation in H.264/AVC. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 2972-2975. 5538025. (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). doi: 10.1109/ISCAS.2010.5538025

@inproceedings{281b615f757c49e58ce83e5e16c93fa4,

title = "A low-power VLSI implementation for variable block size motion estimation in H.264/AVC",

abstract = "Variable block size motion estimation (VBSME) is becoming the new coding technique in H.264/AVC. This paper presents a low-power VLSI implementation for fullsearch VBSME. Compared to existing hardware architectures and implementations for VBSME, the proposed design employs a fast full-search block matching algorithm to reduce power consumption, while preserving the optimal solution and the throughput. The proposed architecture has been implemented and tested in Xilinx XtremeDSP Video Starter Kit Spartan-3ADSP 3400A Edition, and also verified using standard cell approach in UMC 0.18μm CMOS technology. Compared to other VBSME designs that give optimal solutions of Motion Vectors (MV), the proposed design can save power consumption by more than 56%.",

author = "Peng Li and Hua Tang",

year = "2010",

month = aug,

day = "31",

doi = "10.1109/ISCAS.2010.5538025",

language = "English (US)",

isbn = "9781424453085",

series = "ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems",

pages = "2972--2975",

booktitle = "ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems",

note = "2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 ; Conference date: 30-05-2010 Through 02-06-2010",

}

TY - GEN

T1 - A low-power VLSI implementation for variable block size motion estimation in H.264/AVC

AU - Li, Peng

AU - Tang, Hua

PY - 2010/8/31

Y1 - 2010/8/31

N2 - Variable block size motion estimation (VBSME) is becoming the new coding technique in H.264/AVC. This paper presents a low-power VLSI implementation for fullsearch VBSME. Compared to existing hardware architectures and implementations for VBSME, the proposed design employs a fast full-search block matching algorithm to reduce power consumption, while preserving the optimal solution and the throughput. The proposed architecture has been implemented and tested in Xilinx XtremeDSP Video Starter Kit Spartan-3ADSP 3400A Edition, and also verified using standard cell approach in UMC 0.18μm CMOS technology. Compared to other VBSME designs that give optimal solutions of Motion Vectors (MV), the proposed design can save power consumption by more than 56%.

AB - Variable block size motion estimation (VBSME) is becoming the new coding technique in H.264/AVC. This paper presents a low-power VLSI implementation for fullsearch VBSME. Compared to existing hardware architectures and implementations for VBSME, the proposed design employs a fast full-search block matching algorithm to reduce power consumption, while preserving the optimal solution and the throughput. The proposed architecture has been implemented and tested in Xilinx XtremeDSP Video Starter Kit Spartan-3ADSP 3400A Edition, and also verified using standard cell approach in UMC 0.18μm CMOS technology. Compared to other VBSME designs that give optimal solutions of Motion Vectors (MV), the proposed design can save power consumption by more than 56%.

UR - http://www.scopus.com/inward/record.url?scp=77955998027&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77955998027&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2010.5538025

DO - 10.1109/ISCAS.2010.5538025

M3 - Conference contribution

AN - SCOPUS:77955998027

SN - 9781424453085

T3 - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

SP - 2972

EP - 2975

BT - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems

T2 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010

Y2 - 30 May 2010 through 2 June 2010

ER -

A low-power VLSI implementation for variable block size motion estimation in H.264/AVC

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