A low-power VLSI implementation for fast full-search variable block size motion estimation

Peng Li, Hua Tang

Research output: Contribution to journalArticle

2 Scopus citations

Abstract

Variable block size motion estimation (VBSME) is becoming the new coding technique in H.264/AVC. This article presents a low-power VLSI implementation for VBSME, which employs a fast full-search block-matching algorithm to reduce power consumption, while preserving the optimal motion vectors (MVs). The fast full-search algorithm is based on the comparison of the current minimum sum of absolute difference (SAD) to a conservative lower bound so that unnecessary SAD calculations can be eliminated. We first experimentally determine the specific conservative lower bound of SAD and then implement the fast full-search algorithm in FPGA and 0.18 μm CMOS technology. To the best of our knowledge, this is the first time that a fast full-search block-matching algorithm is explored to reduce power consumption in the context of VBSME and implemented in hardware. Experiment results show that the proposed design can save power consumption by 45% compared to conventional VBSME designs that give optimal MV based on the full-search algorithms.

Original languageEnglish (US)
Pages (from-to)1240-1255
Number of pages16
JournalInternational Journal of Electronics
Volume100
Issue number9
DOIs
StatePublished - Sep 1 2013

Keywords

  • H. 264/AVC
  • fast full-search block-matching
  • low-power design
  • variable block size motion estimation

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