A low power fault-tolerance architecture for the kernel density estimation based image segmentation algorithm

The kernel density estimation (KDE)-based image segmentation algorithm has excellent segmentation performance. However, this algorithm is computational intensive. In addition, although this algorithm can tolerant noise in the input images, such as the noise due to snow, rain, or camera shaking, it is sensitive to the noise from the internal computing circuits, such as the noise due to soft errors or PVT (process, voltage, and temperature) variation. Tolerating this kind of noise becomes more and more important as device scaling continues to nanoscale dimensions. Stochastic computing, which uses streams of random bits (stochastic bits streams) to perform computation with conventional digital logic gates, can guarantee reliable computation using unreliable devices. In this paper, we present a stochastic computing implementation of the KDE-based image segmentation algorithm. Our experimental results show that, under the same time constraint, the stochastic implementation is much more tolerant of faults and consumes less hardware and power compared to a conventional (nonstochastic) implementation. Furthermore, compared to a Triple Modular Redundancy (TMR) fault tolerance technique, the stochastic architecture tolerates substantially more soft errors with lower power consumption.