This paper presents a novel hybrid encoding method for encoding of low-density parity-check (LDPC) codes. The design approach is applied to design 10-Gigabit Ethernet transceivers over copper cables. For a specified encoding speed, the proposed method requires substantially lower complexity in terms of area and storage. Furthermore, this method is generic and can be adapted easily for other LDPC codes. One major advantage of this design is that it does not require column swapping and it maintains compatibility with optimized LDPC decoders. For a 10-Gigabit Ethernet transceiver which is compliant with the IEEE 802.3an standard, the proposed sequential (5-Parallel) hybrid architecture has the following implementation properties: critical path: (log2 (324) + 1)Txor + Tand, number of xor gates: 11 056, number of and gates: 1620, and ROM storage: 104 976 bits (which can be minimized to 52 488 bits using additional hardware). This method achieves comparable critical path, and requires 74% gate area, 10% ROM storage as compared with a similar 10-Gigabit sequential (5-Parallel) LDPC encoder design using only the G matrix multiplication method. Additionally the proposed method accesses fewer bits per cycle than the G matrix method which reduces power consumption by about 82%.
Bibliographical noteFunding Information:
Manuscript received June 26, 2008; accepted March 24, 2009. First published May 12, 2009; current version published September 16, 2009. The associate editor coordinating the review of this manuscript and approving it for publication was Prof. An-Yeu Wu. This work was supported by the National Science Foundation under contract 0441632. Parts of this paper have been published in the U. S. Patent Application 20070033485, February 2007 .
- IEEE 802.3an
- Low-density parity check (LDPC)