Abstract
In this paper, we propose a new design for a low complexity floating-point complex multiplier for DSP applications. The design uses a three-term dot-product unit that reduces the overlapped portion found in a previous two-term fused dot-product unit. Comparisons with a primitive fused adder-subtract unit, a dot-product unit and combinations of these primitive units have also been performed. The synthesis results using a 45-nm standard-cell library shows a 16% reduction in area and a 6% reduction in power consumption as compared to a previous complex multiplier using two fused dot-product units.
| Original language | English (US) |
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| Title of host publication | 2014 IEEE International Conference on Signal Processing, Communications and Computing, ICSPCC 2014 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 549-552 |
| Number of pages | 4 |
| ISBN (Electronic) | 9781479952748 |
| DOIs | |
| State | Published - Dec 15 2014 |
| Event | 2014 IEEE International Conference on Signal Processing, Communications and Computing, ICSPCC 2014 - Guilin, Guangxi, China Duration: Aug 5 2014 → Aug 8 2014 |
Publication series
| Name | 2014 IEEE International Conference on Signal Processing, Communications and Computing, ICSPCC 2014 |
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Other
| Other | 2014 IEEE International Conference on Signal Processing, Communications and Computing, ICSPCC 2014 |
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| Country/Territory | China |
| City | Guilin, Guangxi |
| Period | 8/5/14 → 8/8/14 |
Bibliographical note
Publisher Copyright:© 2014 IEEE.
Keywords
- Floating-point complex multiplier
- fused add-subtract
- fused dot product
- three-term fused dot product