Abstract
An efficient architecture of a 64-point FFT processor using two-dimensional algebraic integer (AI) encoding is presented. The advantage of two-dimensional AI encoding is that the hardware complexity for multiplication is reduced since a multiplication can be replaced by a few simple shifts and additions. The ROMless FFT processor, which replaces the ROM for twiddle factors with a twiddle factor generator (TFG) using 2-D AI encoding, has less hardware complexity than previous implementations. The proposed architecture uses a wordlength of 14 bits to achieve an acceptable SNR. It has been synthesized onto an FPGA, and comparative resource utilization results are presented.
Original language | English (US) |
---|---|
Title of host publication | 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings |
Editors | Ru Huang, Ting-Ao Tang, Yu-Long Jiang |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 737-740 |
Number of pages | 4 |
ISBN (Electronic) | 9781467397179 |
DOIs | |
State | Published - 2016 |
Event | 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Hangzhou, China Duration: Oct 25 2016 → Oct 28 2016 |
Publication series
Name | 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings |
---|
Other
Other | 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 |
---|---|
Country/Territory | China |
City | Hangzhou |
Period | 10/25/16 → 10/28/16 |
Bibliographical note
Publisher Copyright:© 2016 IEEE.
Keywords
- AIQ
- FFT/IFFT
- OFDM
- WLAN