In this paper, we analyze a novel sampling technique that addresses the clock jitter problem in high resolution wideband ADCs. The proposed sampler shapes the jitter-induced error in a manner similar to a ΔΣ ADC, which normally shapes the quantization noise. The clock jitter at the sampler is suppressed by the loop filter, and the impact of feedback pulse jitter is reduced through use of switched-capacitor feedback. As opposed to prior studies, we show that the a ΔΣ sampler suppresses the jitter error by more than 10X even at low OSR. As an example, a 2nd-order ΔΣ sampler increases the SJNR by 22 dB at OSR=5, corresponding to more than 3-bit improvement in the achievable SNR. Analysis indicates that increasing the loop order and/or OSR improves the amount of jitter suppression. In addition, the ΔΣ sampler provides the clock programmable anti-aliasing properties of an integration sampler. The analysis was validated via macro-model simulations in MATLAB and circuit simulation in Cadence.
|Original language||English (US)|
|Title of host publication||2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||4|
|State||Published - Feb 2 2017|
|Event||23rd IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016 - Monte Carlo, Monaco|
Duration: Dec 11 2016 → Dec 14 2016
|Name||2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016|
|Other||23rd IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016|
|Period||12/11/16 → 12/14/16|
Bibliographical noteFunding Information:
This research was funded by the DARPA CLASIC program.
© 2016 IEEE.