A holistic analysis of circuit timing variations in 3D-ICs with thermal and TSV-induced stress considerations

Sravan K. Marella, Sanjay V. Kumar, Sachin S. Sapatnekar

Research output: Contribution to journalConference articlepeer-review

14 Scopus citations

Abstract

In 3D ICs, TSV-induced thermal residual stress impacts transistor mobilities due to the piezoresistive effect. This phenomenon is coupled with other temperature effects on transistor parameters that are seen even in the absence of TSVs. In this paper, analytical models are developed to holistically represent the effect of thermally-induced variations on circuit timing. The analysis is based on a semianalytic formulation that is demonstrated to accurately capture the biaxial nature of TSV stress and its effect on delay.

Original languageEnglish (US)
Article number6386629
Pages (from-to)317-324
Number of pages8
JournalIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
StatePublished - Dec 1 2012
Event2012 30th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012 - San Jose, CA, United States
Duration: Nov 5 2012Nov 8 2012

Keywords

  • 3D IC
  • Finite Element Method
  • Static Timing Analysis
  • Through Silicon Via

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