A holistic analysis of circuit timing variations in 3D-ICs with thermal and TSV-induced stress considerations

Sravan K. Marella; Sanjay V. Kumar; Sachin S. Sapatnekar

A holistic analysis of circuit timing variations in 3D-ICs with thermal and TSV-induced stress considerations

Sravan K. Marella, Sanjay V. Kumar, Sachin S. Sapatnekar

Electrical and Computer Engineering

Research output: Contribution to journal › Conference article › peer-review

14 Scopus citations

Abstract

In 3D ICs, TSV-induced thermal residual stress impacts transistor mobilities due to the piezoresistive effect. This phenomenon is coupled with other temperature effects on transistor parameters that are seen even in the absence of TSVs. In this paper, analytical models are developed to holistically represent the effect of thermally-induced variations on circuit timing. The analysis is based on a semianalytic formulation that is demonstrated to accurately capture the biaxial nature of TSV stress and its effect on delay.

Original language	English (US)
Article number	6386629
Pages (from-to)	317-324
Number of pages	8
Journal	IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
State	Published - Dec 1 2012
Event	2012 30th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012 - San Jose, CA, United States Duration: Nov 5 2012 → Nov 8 2012

Keywords

3D IC
Finite Element Method
Static Timing Analysis
Through Silicon Via

Cite this

A holistic analysis of circuit timing variations in 3D-ICs with thermal and TSV-induced stress considerations. / Marella, Sravan K.; Kumar, Sanjay V.; Sapatnekar, Sachin S.

In: IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 01.12.2012, p. 317-324.

Research output: Contribution to journal › Conference article › peer-review

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AB - In 3D ICs, TSV-induced thermal residual stress impacts transistor mobilities due to the piezoresistive effect. This phenomenon is coupled with other temperature effects on transistor parameters that are seen even in the absence of TSVs. In this paper, analytical models are developed to holistically represent the effect of thermally-induced variations on circuit timing. The analysis is based on a semianalytic formulation that is demonstrated to accurately capture the biaxial nature of TSV stress and its effect on delay.

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KW - Static Timing Analysis

KW - Through Silicon Via

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A holistic analysis of circuit timing variations in 3D-ICs with thermal and TSV-induced stress considerations

Abstract

Keywords

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