TY - JOUR
T1 - A Holistic Analysis of Circuit Performance Variations in 3-D ICs with Thermal and TSV-Induced Stress Considerations
AU - Marella, Sravan K.
AU - Sapatnekar, Sachin S.
N1 - Publisher Copyright:
© 1993-2012 IEEE.
PY - 2015/7/1
Y1 - 2015/7/1
N2 - In 3-D ICs, through silicon via (TSV)-induced thermal residual stress impacts several transistor electrical parameters - low-field mobility, saturation velocity, and threshold voltage. These thermal-stress related shifts are coupled with other temperature effects on transistor parameters that are seen even in the absence of TSVs. In this paper, analytical models are developed to holistically represent the effect of thermally-induced variations on circuit timing. A biaxial stress model is built, based on a superposition of 2-D axisymmetric and Boussinesq-type elasticity models. The computed stresses and strains are then employed to evaluate transistor mobility, saturation velocity, and threshold voltage. The electrical variations are translated into gate-level delay and leakage power calculations, which are then elevated to circuit-level analysis to thoroughly evaluate the variations in circuit performance-induced by TSV stress.
AB - In 3-D ICs, through silicon via (TSV)-induced thermal residual stress impacts several transistor electrical parameters - low-field mobility, saturation velocity, and threshold voltage. These thermal-stress related shifts are coupled with other temperature effects on transistor parameters that are seen even in the absence of TSVs. In this paper, analytical models are developed to holistically represent the effect of thermally-induced variations on circuit timing. A biaxial stress model is built, based on a superposition of 2-D axisymmetric and Boussinesq-type elasticity models. The computed stresses and strains are then employed to evaluate transistor mobility, saturation velocity, and threshold voltage. The electrical variations are translated into gate-level delay and leakage power calculations, which are then elevated to circuit-level analysis to thoroughly evaluate the variations in circuit performance-induced by TSV stress.
KW - 3-D IC
KW - finite element method (FEM)
KW - static timing analysis
KW - through silicon via (TSV)
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U2 - 10.1109/TVLSI.2014.2335154
DO - 10.1109/TVLSI.2014.2335154
M3 - Article
AN - SCOPUS:85027924697
SN - 1063-8210
VL - 23
SP - 1308
EP - 1321
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 7
M1 - 6870451
ER -