A Holistic Analysis of Circuit Performance Variations in 3-D ICs with Thermal and TSV-Induced Stress Considerations

Sravan K. Marella, Sachin S. Sapatnekar

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25 Scopus citations

Abstract

In 3-D ICs, through silicon via (TSV)-induced thermal residual stress impacts several transistor electrical parameters - low-field mobility, saturation velocity, and threshold voltage. These thermal-stress related shifts are coupled with other temperature effects on transistor parameters that are seen even in the absence of TSVs. In this paper, analytical models are developed to holistically represent the effect of thermally-induced variations on circuit timing. A biaxial stress model is built, based on a superposition of 2-D axisymmetric and Boussinesq-type elasticity models. The computed stresses and strains are then employed to evaluate transistor mobility, saturation velocity, and threshold voltage. The electrical variations are translated into gate-level delay and leakage power calculations, which are then elevated to circuit-level analysis to thoroughly evaluate the variations in circuit performance-induced by TSV stress.

Original languageEnglish (US)
Article number6870451
Pages (from-to)1308-1321
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume23
Issue number7
DOIs
StatePublished - Jul 1 2015

Bibliographical note

Publisher Copyright:
© 1993-2012 IEEE.

Keywords

  • 3-D IC
  • finite element method (FEM)
  • static timing analysis
  • through silicon via (TSV)

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