A high-throughput LDPC decoder architecture for high-rate WPAN systems

Kyung Il Baek, Hanho Lee, Chang Seok Choi, Sangmin Kim, Gerald E. Sobelman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a high-throughput memory-efficient decoder architecture for Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes in the high-rate wireless personal area network applications. Two novel techniques which can apply to our selected QC-LDPC codes are proposed, including four-parallel block layered decoding architecture and simplification of the switch networks. The proposed architecture based on a block parallel decoding scheme replaces a crossbar-based interconnect network with a fixed wire network for a switch network. In addition, two-stage pipelining is used to improve the clock speed. A 672-bit, rate-1/2 LDPC decoder is implemented using 90 nm CMOS technology. The design achieves an information throughput of 1.45 Gbps at a clock speed of 285 MHz with a maximum of 16 iterations.

Original languageEnglish (US)
Title of host publication2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
Pages1311-1314
Number of pages4
DOIs
StatePublished - Aug 2 2011
Event2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 - Rio de Janeiro, Brazil
Duration: May 15 2011May 18 2011

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

Other2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
CountryBrazil
CityRio de Janeiro
Period5/15/115/18/11

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  • Cite this

    Baek, K. I., Lee, H., Choi, C. S., Kim, S., & Sobelman, G. E. (2011). A high-throughput LDPC decoder architecture for high-rate WPAN systems. In 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 (pp. 1311-1314). [5937812] (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2011.5937812